Datasheet

DocID028094 Rev 5 105/142
STM32F410x8/B Electrical characteristics
118
Figure 32. SPI timing diagram - slave mode and CPHA = 0
t
a(SO
) Data output access time Slave mode 7 - 21 ns
t
dis(SO)
Data output disable time Slave mode 5 - 12 ns
t
v(SO)
Data output valid time
Slave mode (after enable edge),
2.7 V < V
DD
< 3.6 V
-1113ns
Slave mode (after enable edge),
1.7 V < V
DD
< 3.6 V
- 11 18.5 ns
t
h(SO)
Data output hold time
Slave mode (after enable edge),
1.7 V < V
DD
< 3.6 V
8--ns
t
v(MO)
Data output valid time Master mode (after enable edge) - 4 6 ns
t
h(MO)
Data output hold time
Master mode (after enable edge) 0 - - ns
1. Guaranteed by characterization.
2. Maximum frequency in Slave transmitter mode is determined by the sum of t
v(SO)
and t
su(MI)
which has to fit into SCK low or
high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master
having t
su(MI)
= 0 while Duty(SCK) = 50%
Table 64. SPI dynamic characteristics
(1)
(continued)
Symbol Parameter Conditions Min Typ Max Unit
DLF
6&.,QSXW
166LQSXW
W
68166
W F6&.
W K166
&3+$ 
&32/ 
&3+$ 
&32/ 
W
Z6&.+
W Z6&./
W 962 W K62
W U6&.
W I6&.
W GLV62
W D62
0,62
287387
026,
,1387
06%287 %,7287 /6%287
W
VX6,
W K6,
06%,1
%,7,1 /6%,1
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