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This is information on a product in full production.

April 2017 DocID028094 Rev 5 1/142

STM32F410x8 STM32F410xB

ARM

-Cortex

-M4 32b MCU+FPU, 125 DMIPS, 128KB Flash,

32KB RAM, 9 TIMs, 1 ADC, 1 DAC, 1 LPTIM, 9 comm. interfaces

Datasheet - production data

Features

• Dynamic Efficiency Line with eBAM (enhanced

Batch Acquisition Mode)

– 1.7 V to 3.6 V power supply

– -40 °C to 85/105/125 °C temperature range

• Core: ARM

32-bit Cortex

-M4 CPU with FPU,

Adaptive real-time accelerator (ART

Accelerator™) allowing 0-wait state execution

from Flash memory, frequency up to 100 MHz,

memory protection unit,

125 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1),

and DSP instructions

• Memories

– Up to 128 Kbytes of Flash memory

– 512 bytes of OTP memory

– 32 Kbytes of SRAM

• Clock, reset and supply management

– 1.7 V to 3.6 V application supply and I/Os

– POR, PDR, PVD and BOR

– 4-to-26 MHz crystal oscillator

– Internal 16 MHz factory-trimmed RC

– 32 kHz oscillator for RTC with calibration

– Internal 32 kHz RC with calibration

• Power consumption

– Run: 89 µA/MHz (peripheral off)

– Stop (Flash in Stop mode, fast wakeup

time): 40 µA Typ @ 25 °C; 49 µA max

@25 °C

– Stop (Flash in Deep power down mode,

slow wakeup time): down to 6 µA @ 25 °C;

14 µA max @25 °C

– Standby: 2.4 µA @25 °C / 1.7 V without

RTC; 12 µA @85 °C @1.7 V

–V

BAT

supply for RTC: 1 µA @25 °C

• 1×12-bit, 2.4 MSPS ADC: up to 16 channels

• 1×12-bit D/A converter

• General-purpose DMA: 16-stream DMA

controllers with FIFOs and burst support

• Up to 9 timers

– One low-power timer (available in Stop

mode)

– One 16-bit advanced motor-control timer

– Three 16-bit general purpose timers

– One 32-bit timer up to 100 MHz with up to

four IC/OC/PWM or pulse counter and

quadrature (incremental) encoder input

– Two watchdog timers (independent

window)

– SysTick timer.

• Debug mode

– Serial wire debug (SWD) & JTAG

interfaces

–Cortex

-M4 Embedded Trace Macrocell™

• Up to 50 I/O ports with interrupt capability

– Up to 45 fast I/Os up to 100 MHz

– Up to 49 5 V-tolerant I/Os

• Up to 9 communication interfaces

– Up to 3x I

C interfaces (SMBus/PMBus)

including 1x I

C Fast-mode at 1 MHz

– Up to 3 USARTs (2 x 12.5 Mbit/s,

1 x 6.25 Mbit/s), ISO 7816 interface, LIN,

IrDA, modem control)

– Up to 3 SPI/I2Ss (up to 50 Mbit/s SPI or

I2S audio protocol)

• True random number generator

• CRC calculation unit

• 96-bit unique ID

• RTC: subsecond accuracy, hardware calendar

• All packages are ECOPACK

Table 1. Device summary

Reference Part number

STM32F410x8

STM32F410T8, STM32F410C8,

STM32F410R8

STM32F410xB

STM32F410TB, STM32F410CB,

STM32F410RB

WLCSP36

UFQFPN48

(7×7mm)

(2.553x2.579mm)

LQFP48 (7x7mm)

&"'!

UFBGA64

(

5x5mm

)

LQFP64 (10×10mm)

www.st.com

Downloaded from Arrow.com.

Summary of content (142 pages)

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STM32F410x8 STM32F410xB ARM®-Cortex®-M4 32b MCU+FPU, 125 DMIPS, 128KB Flash, 32KB RAM, 9 TIMs, 1 ADC, 1 DAC, 1 LPTIM, 9 comm. interfaces Datasheet - production data Features &"'! • Dynamic Efficiency Line with eBAM (enhanced Batch Acquisition Mode) – 1.7 V to 3.
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Contents STM32F410x8/B Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 3 Compatibility with STM32F4 series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.
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STM32F410x8/B Contents 3.20.4 Low-power timer (LPTIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.20.5 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.20.6 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.20.7 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.21 Inter-integrated circuit interface (I2C) . .
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Contents 7 STM32F410x8/B 6.3.6 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.3.7 Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.3.8 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.3.9 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.3.10 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . .
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STM32F410x8/B Contents B.2 Batch Acquisition Mode (BAM) example . . . . . . . . . . . . . . . . . . . . . . . . . 139 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 DocID028094 Rev 5 5/142 5 Downloaded from Arrow.com.
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List of tables STM32F410x8/B List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. 6/142 Downloaded from Arrow.com. Device summary . . . . . . . . . . . .
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STM32F410x8/B Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88.
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List of tables Table 89. 8/142 Downloaded from Arrow.com. STM32F410x8/B Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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STM32F410x8/B List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43.
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List of figures Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. 10/142 Downloaded from Arrow.com. STM32F410x8/B package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 UFQFPN48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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STM32F410x8/B 1 Introduction Introduction This datasheet provides the description of the STM32F410x8/B microcontrollers. For information on the Cortex®-M4 core, please refer to the Cortex®-M4 programming manual (PM0214) available from www.st.com. DocID028094 Rev 5 11/142 31 Downloaded from Arrow.com.
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Description 2 STM32F410x8/B Description The STM32F410X8/B devices are based on the high-performance ARM® Cortex® -M4 32bit RISC core operating at a frequency of up to 100 MHz. Their Cortex®-M4 core features a Floating point unit (FPU) single precision which supports all ARM single-precision dataprocessing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security.
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STM32F410x8/B Description Table 2.
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Description 2.1 STM32F410x8/B Compatibility with STM32F4 series The STM32F410x8/B are fully software and feature compatible with the STM32F4 series (STM32F42x, STM32F401, STM32F43x, STM32F41x, STM32F405 and STM32F407) The STM32F410x8/B can be used as drop-in replacement of the other STM32F4 products but some slight changes have to be done on the PCB board. Figure 1.
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STM32F410x8/B Description Figure 2. STM32F410x8/B block diagram -7567 -7', -7&. 6:&/. -7'2 6:' -7'2 75$&(&/. 75$&('> @ -7$* 6: 038 )38 (70 19,& , %86 $50 &RUWH[ 0 &RUWH[ 0 0+] .% 65$0 ' %86 $+% EXV PDWUL[ 6 0 $&&(/ &$&+( 6 %86 .% )ODVK PHPRU\ 51* 3RZHU PDQDJPW 9'' 9ROWDJH UHJXODWRU WR 9 6WUHDPV '0$ ),)2 $+% 0+] 6WUHDPV '0$ ),)2 #9''$ 3$> @ #9'' 5& +6 *3,2 3257 $ 3%> @ *3,2 3257 % *3,2 3257 & 3+> @ *3,2 3257 + 6XSSO\ VXSHUY
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Functional overview STM32F410x8/B 3 Functional overview 3.1 ARM® Cortex®-M4 with FPU core with embedded Flash and SRAM The ARM® Cortex®-M4 with FPU processor is the latest generation of ARM processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts.
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STM32F410x8/B 3.4 Functional overview Memory protection unit The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory.
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Functional overview 3.8 STM32F410x8/B Multi-AHB bus matrix The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs) and the slaves (Flash memory, RAM, AHB and APB peripherals) and ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously. Figure 3. Multi-AHB matrix 6 6 6 '0$B3 *3 '0$ '0$B0(0 '0$B0(0 '0$B3, 6 EXV 6 *3 '0$ 6 0 ,&2'( 0 '&2'( $&&(/ 6 ' EXV , EXV $50 &RUWH[ 0 )ODVK .% 0 65$0 .E\WHV 0
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STM32F410x8/B 3.10 Functional overview Nested vectored interrupt controller (NVIC) The devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 62 maskable interrupt channels plus the 16 interrupt lines of the Cortex®-M4 with FPU.
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Functional overview 3.13 STM32F410x8/B Boot modes At startup, boot pins are used to select one out of three boot options: • Boot from user Flash • Boot from system memory • Boot from embedded SRAM The bootloader is located in system memory. It is used to reprogram the Flash memory by using the interfaces described in Table 3. Refer to Table 9: STM32F410x8/B pin definitions) for the GPIOs available on the selected package.
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STM32F410x8/B Functional overview 3.15 Power supply supervisor 3.15.1 Internal reset ON This feature is available for VDD operating voltage range 1.8 V to 3.6 V. The internal power supply supervisor is enabled by holding PDR_ON high. The device has an integrated power-on reset (POR) / power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry. At power-on, POR is always active, and ensures proper operation starting from 1.8 V. After the 1.
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Functional overview STM32F410x8/B A comprehensive set of power-saving mode allows to design low-power applications. When the internal reset is OFF, the following integrated features are no longer supported: 3.16 • The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled. • The brownout reset (BOR) circuitry must be disabled. • The embedded programmable voltage detector (PVD) is disabled. • VBAT functionality is no more available and VBAT pin should be connected to VDD.
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STM32F410x8/B 3.17 Functional overview Real-time clock (RTC) and backup registers The backup domain includes: • The real-time clock (RTC) • 20 backup registers The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binarycoded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are performed automatically.
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Functional overview STM32F410x8/B and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low-power mode. The RTC and the low-power timer (LPTIM1) can remain active in Stop mode. They can consequently be used to wake up the device from this mode. The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line source can be one of the 16 external lines, the PVD output, LPTIM1, the RTC alarm/ wakeup/ tamper/ time stamp events).
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STM32F410x8/B Functional overview Table 5. Timer feature comparison Timer type Advanced -control Complementary output Max. interface clock (MHz) Max.
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Functional overview 3.20.1 STM32F410x8/B Advanced-control timers (TIM1) The advanced-control timer (TIM1) can be seen as three-phase PWM generator multiplexed on 4 independent channels. It has complementary PWM outputs with programmable inserted dead times. It can also be considered as a complete general-purpose timer.
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STM32F410x8/B 3.20.4 Functional overview Low-power timer (LPTIM1) The devices embed one low-power timer. This timer features an independent clock and runs in Stop mode if it is clocked by LSE, LSI or by an external clock. It is able to wake up the system from Stop mode. The low-power timer main features are the following: 3.20.
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Functional overview 3.21 STM32F410x8/B Inter-integrated circuit interface (I2C) The devices feature up to three I2C bus interfaces which can operate in multimaster and slave modes: • One I2C interface supports the Standard mode (up to 100 kHz), Fast-mode (up to 400 kHz) modes and Fast-mode plus (up to 1 MHz). • Two I2C interfaces support the Standard mode (up to 100 KHz) and the Fast mode (up to 400 KHz). Their frequency can be increased up to 1 MHz.
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STM32F410x8/B Functional overview Table 7. USART feature comparison Max. baud Max. baud USART Standard Modem SPI Smartcard rate in Mbit/s rate in Mbit/s APB LIN irDA name features (RTS/CTS) master (ISO 7816) (oversampling (oversampling mapping by 16) by 8) USART1 X X(1) X X X X 6.25 12.5 APB2 (max. 100 MHz) USART2 X X(1) X X(1) X X(1) 3.12 6.25 APB1 (max. 50 MHz) X N.A X X(1)(2) X X(1)(2) 6.25 12.5 APB2 (max. 50 MHz) USART6 (1) 1. Not available on WLCSP36 package. 2.
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Functional overview 3.26 STM32F410x8/B General-purpose input/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain, with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions.
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STM32F410x8/B Functional overview • Triangular-wave generation • DMA capability for each channel • External triggers for conversion • Sample and hold low-power mode, with internal or external capacitor The DAC channel is triggered through TIM6 update output that is also connected to different DMA channels. 3.
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Pinouts and pin description 4 STM32F410x8/B Pinouts and pin description 9'' 3'5B21 966 3% %227 3% 3% 3% 3% 3% 3$ 3$ Figure 5. LQFP48 pinout 9%$7 9'' 3& $17,B7$03 966 3& 26& B,1 3$ 3& 26& B287 3$ 3+ 26&B,1 3$ 3+ 26&B287 3$ 1567 3$ 966$ 95() 3$ 9''$ 95() 3% 3$ :.
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STM32F410x8/B Pinouts and pin description 3$ 9'' 3& 966 3& 26& B,1 3$ 3& 26& B287 3$ 3+ 26&B,1 3$ 3+ 26&B287 3$ 1567 3$ 966$ 95() 3$ 9''$ 95() 3% 3% 3$ 3% 3$ 3% 966 9'' 3$ 3% 3% 3% 3% 3% %227 3% 3% 3% 3% 3% 3$ 3% 3$ 3$ 966 3$ 9%$
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Pinouts and pin description STM32F410x8/B Figure 9. WLCSP36 pinout $ 9'' 966 3% 3% 3$ 9'' % 3& 26& B,1 9%$7 3'5B 21 3% 3$ 966 & 3& 26& B 287 3+ 26&B,1 3& 3% 3% 3$ ' 3+ 26&B287 1567 %227 3% 3$ 3$ ( 966$ 95() 3$ 3$ 3% 9&$3 B 3% ) 9''$ 95() 3$ 3$ 3% 966 9'' 06Y 9 1. The above figure shows the package bump side. Table 8.
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STM32F410x8/B Pinouts and pin description Table 9.
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Pinouts and pin description STM32F410x8/B 12 16 F3 PA2 Pin type UFBGA64 LQFP64 UFQFPN48 12 Pin name (function after reset)(1) I/O FT Notes E4 LQFP48 WLCSP36 Pin Number I/O structure Table 9.
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STM32F410x8/B Pinouts and pin description 21 29 G7 PB10 I/O FT - E2 22 22 30 H7 VCAP_1 S - - - - F2 23 23 31 D6 VSS S - - - - F1 24 24 32 E5 VDD S - - - - - TIM1_BKIN, TIM5_CH1, I2C2_SMBA, SPI2_NSS/I2S2_WS, EVENTOUT - - TIM1_CH1N, I2C4_SMBA, SPI2_SCK/I2S2_CK, EVENTOUT - - TIM1_CH2N, I2C4_SDA, SPI2_MISO, EVENTOUT - - RTC_50Hz, TIM1_CH3N, I2C4_SCL, SPI2_MOSI/I2S2_SD, EVENTOUT - - TRACECLK, I2C4_SCL, I2S2_MCK, USART6_TX, EVENTOUT - - E1 - - - 25 26
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Pinouts and pin description STM32F410x8/B 29 41 C8 PA8 I/O FT - - 30 30 42 B8 PA9 I/O FT - TIM1_CH2, USART1_TX, EVENTOUT - - TIM1_CH3, SPI5_MOSI/I2S5_SD, USART1_RX, EVENTOUT - - TIM1_CH4, USART1_CTS, USART6_TX, EVENTOUT - - - - 31 32 31 32 43 44 UFBGA64 29 LQFP64 D1 MCO_1, TIM1_CH1, I2C4_SCL, USART1_CK, EVENTOUT LQFP48 Alternate functions WLCSP36 Notes Pin name (function after reset)(1) Pin type UFQFPN48 Pin Number I/O structure Table 9.
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STM32F410x8/B Pinouts and pin description - - B5 PB11 Pin type UFBGA64 LQFP64 54 Pin name (function after reset)(1) I/O FT Notes - UFQFPN48 LQFP48 WLCSP36 Pin Number I/O structure Table 9.
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Pinouts and pin description STM32F410x8/B 2. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: - The speed should not exceed 2 MHz with a maximum load of 30 pF. - These I/Os must not be used as a current source (e.g. to drive an LED). 3. Main function after the first backup domain power-up.
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Memory mapping 5 STM32F410x8/B Memory mapping The memory map is shown in Figure 10. Figure 10. Memory map 5HVHUYHG [( [)))) )))) &RUWH[ 0 LQWHUQDO [( [( ) )))) SHULSKHUDOV ['))) )))) 5HVHUYHG [ [ )) [)))) )))) [( ['))) )))) 0E\WH EORFN &RUWH[ 0 V LQWHUQDO SHULSKHUDOV $+% 0E\WH EORFN 1RW XVHG [& [%))) )))) 5HVHUYHG [ [ [ )))) [ )) 5HVHUYHG [ [ ))) )))) $3% 0E\WH EO
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STM32F410x8/B Memory mapping Table 11.
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Memory mapping STM32F410x8/B Table 11. STM32F410x8/B register boundary addresses(1) Bus APB2 46/142 Downloaded from Arrow.com.
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STM32F410x8/B Memory mapping Table 11.
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Electrical characteristics STM32F410x8/B 6 Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range).
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STM32F410x8/B 6.1.5 Electrical characteristics Pin input voltage The input voltage measurement on a pin of the device is described in Figure 12. Figure 12. Input voltage measurement -#5 PIN 6). -3 6 DocID028094 Rev 5 49/142 118 Downloaded from Arrow.com.
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Electrical characteristics 6.1.6 STM32F410x8/B Power supply scheme Figure 13.
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STM32F410x8/B 6.1.7 Electrical characteristics Current consumption measurement Figure 14. Current consumption measurement scheme ,''B9%$7 9%$7 ,'' 9'' 9''$ DL 6.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 12: Voltage characteristics, Table 13: Current characteristics, and Table 14: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied.
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Electrical characteristics STM32F410x8/B Table 13. Current characteristics Symbol Ratings Max.
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STM32F410x8/B Electrical characteristics 6.3 Operating conditions 6.3.1 General operating conditions Table 15.
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Electrical characteristics STM32F410x8/B Table 15.
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STM32F410x8/B Electrical characteristics Table 16. Features depending on the operating power supply range Operating power supply range ADC operation VDD =1.7 to 2.1 V(4) Conversion time up to 1.2 Msps VDD = 2.1 to 2.4 V Conversion time up to 1.2 Msps VDD = 2.4 to 2.7 V Conversion time up to 2.4 Msps VDD = 2.7 to 3.6 V Conversion time up to 2.
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Electrical characteristics 6.3.2 STM32F410x8/B VCAP_1 external capacitor Stabilization for the main regulator is achieved by connecting the external capacitor CEXT to the VCAP_1 pin. CEXT is specified in Table 17. Figure 15. External capacitor CEXT & (65 5 /HDN 06 9 1. Legend: ESR is the equivalent series resistance. Table 17. VCAP_1 operating conditions 6.3.3 Symbol Parameter Conditions CEXT Capacitance of external capacitor 4.
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STM32F410x8/B 6.3.5 Electrical characteristics Embedded reset and power control block characteristics The parameters given in Table 20 are derived from tests performed under ambient temperature and VDD supply voltage @ 3.3V. Table 20. Embedded reset and power control block characteristics Symbol Parameter Conditions Programmable voltage detector level selection VPVD VPVDhyst(2) PVD hysteresis VPOR/PDR Typ Max PLS[2:0]=000 (rising edge) 2.09 2.14 2.19 PLS[2:0]=000 (falling edge) 1.98 2.
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Electrical characteristics STM32F410x8/B Table 20. Embedded reset and power control block characteristics (continued) Symbol IRUSH(2) ERUSH (2) Parameter Conditions Min Typ Max Unit In-Rush current on voltage regulator poweron (POR or wakeup from Standby) - 160 200 mA In-Rush energy on voltage regulator power- VDD = 1.7 V, TA = 125 °C, on (POR or wakeup from IRUSH = 171 mA for 31 µs Standby) - - 5.4 µC 1. The product behavior is guaranteed by design down to the minimum VPOR/PDR value.
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STM32F410x8/B Electrical characteristics Table 21. Typical and maximum current consumption, code with data processing (ART accelerator disabled) running from SRAM - VDD = 1.
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Electrical characteristics STM32F410x8/B Table 22. Typical and maximum current consumption, code with data processing (ART accelerator disabled) running from SRAM - VDD = 3.
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STM32F410x8/B Electrical characteristics Table 23. Typical and maximum current consumption in run mode, code with data processing (ART accelerator enabled except prefetch) running from Flash memory- VDD = 1.
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Electrical characteristics STM32F410x8/B Table 24. Typical and maximum current consumption in run mode, code with data processing (ART accelerator enabled except prefetch) running from Flash memory - VDD = 3.
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STM32F410x8/B Electrical characteristics Table 25. Typical and maximum current consumption in run mode, code with data processing (ART accelerator disabled) running from Flash memory - VDD = 3.
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Electrical characteristics STM32F410x8/B Table 26. Typical and maximum current consumption in run mode, code with data processing (ART accelerator disabled) running from Flash memory - VDD = 1.
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STM32F410x8/B Electrical characteristics Table 27. Typical and maximum current consumption in run mode, code with data processing (ART accelerator enabled with prefetch) running from Flash memory - VDD = 3.
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Electrical characteristics STM32F410x8/B Table 28. Typical and maximum current consumption in Sleep mode - VDD = 3.
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STM32F410x8/B Electrical characteristics Table 28. Typical and maximum current consumption in Sleep mode - VDD = 3.
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Electrical characteristics STM32F410x8/B Table 29. Typical and maximum current consumption in Sleep mode - VDD = 1.
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STM32F410x8/B Electrical characteristics Table 29. Typical and maximum current consumption in Sleep mode - VDD = 1.
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Electrical characteristics STM32F410x8/B Table 30. Typical and maximum current consumptions in Stop mode - VDD = 1.7 V Typ Symbol Conditions Max TA = TA = TA = TA = TA = 25 °C 25 °C(1) 85 °C 105 °C(1) 125 °C(1) Flash in Stop mode, Main regulator usage 105.6 all oscillators OFF, no independent Low power regulator usage 39.
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STM32F410x8/B Electrical characteristics Table 33. Typical and maximum current consumption in Standby mode - VDD= 3.6 V Typ Symbol Parameter Conditions IDD_STBY Supply current in Standby mode Low-speed oscillator (LSE) and RTC ON RTC and LSE OFF Max TA = 25 °C TA = 25 °C(1) 3.4 4.3 (2) 2.5 3.3 TA = TA = TA = 85 °C 105 °C(1) 125 °C(1) 8.9 7.8 22.8 21.6 (3) 65.0 64.0 Uni t µA (2) 1. Guaranteed by characterization, unless otherwise specified. 2. Guaranteed by tests in production. 3.
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Electrical characteristics STM32F410x8/B Figure 16. Typical VBAT current consumption (LSE and RTC ON/LSE oscillator in “low power” mode selection ,''B9%$7 $ 7HPSHUDWXUH & 06 9 Figure 17.
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STM32F410x8/B Electrical characteristics trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs. Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise.
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Electrical characteristics STM32F410x8/B Table 35. Switching output I/O current consumption Symbol Parameter Conditions(1) VDD = 3.3 V C = CINT VDD = 3.3 V CEXT = 0 pF C = CINT + CEXT + CS IDDIO I/O switching current VDD = 3.3 V CEXT =10 pF C = CINT + CEXT + CS VDD = 3.3 V CEXT = 22 pF C = CINT + CEXT + CS VDD = 3.3 V CEXT = 33 pF C = CINT + CEXT + CS I/O toggling Typ frequency (fSW) 2 MHz 0.05 8 MHz 0.15 25 MHz 0.45 50 MHz 0.85 60 MHz 1.00 84 MHz 1.40 90 MHz 1.67 2 MHz 0.
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STM32F410x8/B Electrical characteristics On-chip peripheral current consumption The MCU is placed under the following conditions: • At startup, all I/O pins are in analog input configuration. • All peripherals are disabled unless otherwise mentioned. • The ART accelerator is ON. • Voltage Scale 2 mode selected, internal digital voltage V12 = 1.26 V. • HCLK is the system clock at 100 MHz. fPCLK1 = fHCLK/2, and fPCLK2 = fHCLK.
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Electrical characteristics STM32F410x8/B Table 36. Peripheral current consumption (continued) IDD (Typ) Peripheral APB2 (up to 100 MHz) Voltage scale1 Voltage scale2 Voltage scale3 APB2 to AHB 0,22 0,19 0,17 TIM1 6,62 6,36 5,66 USART1 3,19 3,10 2,77 USART6 3,10 2,99 2,66 ADC1 3,35 3,25 2,88 SPI1/I2S1 1,82 1,77 1,58 SYSCFG 0,83 0,81 0,72 EXTI 0,92 0,88 0,80 TIM9 2,90 2,81 2,48 TIM11 2,13 2,06 1,81 SPI5/I2S5 1,88 1,83 1,59 1.91 1.82 1.64 Bus matrix 1.
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STM32F410x8/B 6.3.7 Electrical characteristics Wakeup time from low-power modes The wakeup times given in Table 37 are measured starting from the wakeup event trigger up to the first instruction executed by the CPU: • For Stop or Sleep modes: the wakeup event is WFE. • WKUP (PA0) pin is used to wakeup from Standby, Stop and Sleep modes. Figure 18. Low-power mode wakeup :DNHXS IURP 6WRS PRGH PDLQ UHJXODWRU 2SWLRQ E\WHV DUH QRW UHORDGHG &38 UHVWDUW 5HJXODWRU +6, UHVWDUW )ODVK VWRS H[LW UDPS XS :DNH
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Electrical characteristics STM32F410x8/B Table 37. Low-power mode wakeup timings(1) Symbol Parameter Min Typ Max Unit - - 4 6 CPU clock cycles Flash memory in Deep power down mode - - 40,0 Main regulator - 12.9 15.0 - 104.9 115.0 - 20.8 25.0 - 112.9 120.0 Main regulator, Flash memory in Stop or Deep power down mode - 4.9 7.0 Regulator in low-power mode, Flash memory in Stop or Deep power down mode(3) - 12.8 20.0 Wakeup from Standby mode - - 316.8 350.
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STM32F410x8/B Electrical characteristics Table 38. High-speed external user clock characteristics Symbol Parameter Conditions fHSE_ext External user clock source frequency(1) VHSEH OSC_IN input pin high level voltage VHSEL OSC_IN input pin low level voltage tw(HSE) tw(HSE) OSC_IN high or low time(1) Min Typ Max Unit 1 - 50 MHz 0.7VDD - VDD VSS - 0.
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Electrical characteristics STM32F410x8/B Figure 19. High-speed external clock source AC timing diagram 6(3%( 6(3%, TR (3% TF (3% T7 (3% /3#?). ), T7 (3% T 4(3% %XTERNAL CLOCK SOURCE F(3%?EXT 34- & AI Figure 20.
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STM32F410x8/B Electrical characteristics Table 40. HSE 4-26 MHz oscillator characteristics(1) Symbol fOSC_IN RF IDD Parameter Conditions Min Typ Max Unit Oscillator frequency - 4 - 26 MHz Feedback resistor - - 200 - kΩ VDD=3.3 V, ESR= 30 Ω, CL=5 pF @25 MHz - 450 - VDD=3.3 V, ESR= 30 Ω, CL=10 pF @25 MHz - 530 - Startup - - 1 mA/V VDD is stabilized - 2 - ms HSE current consumption Gm_crit_max Maximum critical crystal gm tSU(HSE)(2) Startup time µA 1.
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Electrical characteristics STM32F410x8/B The LSE high-power mode allows to cover a wider range of possible crystals but with a cost of higher power consumption. Table 41. LSE oscillator characteristics (fLSE = 32.768 kHz) (1) Symbol Parameter RF Feedback resistor IDD LSE current consumption Gm_crit_max Maximum critical crystal gm tSU(LSE)(2) startup time Conditions Min Typ Max Unit - - 18.
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STM32F410x8/B 6.3.9 Electrical characteristics Internal clock source characteristics The parameters given in Table 42 and Table 43 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 15. High-speed internal (HSI) RC oscillator Table 42. HSI oscillator characteristics (1) L Symbol fHSI Parameter Frequency Conditions Min Typ Max Unit - - 16 - MHz - - 1 % –8 - 5.
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Electrical characteristics STM32F410x8/B Low-speed internal (LSI) RC oscillator Table 43. LSI oscillator characteristics (1) Symbol Parameter fLSI(2) tsu(LSI) Min Typ Max Unit 17 32 47 kHz LSI oscillator startup time - 15 40 µs LSI oscillator power consumption - 0.4 0.6 µA Frequency (3) IDD(LSI)(3) 1. VDD = 3 V, TA = –40 to 125 °C unless otherwise specified. 2. Guaranteed by characterization. 3. Guaranteed by design. Figure 24. ACCLSI versus temperature MAX AVG MIN .
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STM32F410x8/B Electrical characteristics Table 44. Main PLL characteristics (continued) Symbol tLOCK Parameter Conditions PLL lock time Min Typ Max VCO freq = 100 MHz 75 - 200 VCO freq = 432 MHz 100 - 300 - 25 - - ±150 - - 15 - - ±200 - - 0.40 0.75 - 0.40 0.85 RMS Cycle-to-cycle jitter System clock 100 MHz Jitter(3) peak to peak RMS peak to peak Period Jitter IDD(PLL)(4) PLL power consumption on VDD VCO freq = 100 MHz VCO freq = 432 MHz 0.15 0.
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Electrical characteristics 6.3.11 STM32F410x8/B PLL spread spectrum clock generation (SSCG) characteristics The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic interferences (see Table 51: EMI characteristics for LQFP64). It is available only on the main PLL. Table 45. SSCG parameter constraints Symbol Parameter Min Typ Max(1) Unit fMod Modulation frequency - - 10 kHz md Peak modulation depth 0.
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STM32F410x8/B Electrical characteristics Figure 25 and Figure 26 show the main PLL output clock waveforms in center spread and down spread modes, where: F0 is fPLL_OUT nominal. Tmode is the modulation period. md is the modulation depth. Figure 25. PLL output clock waveforms in center spread mode &REQUENCY 0,,?/54 MD & MD TMODE 4IME XTMODE AI Figure 26. PLL output clock waveforms in down spread mode )UHTXHQF\ 3//B287 ) [PG WPRGH 7LPH [WPRGH DL E 6.3.
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Electrical characteristics STM32F410x8/B Table 47.
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STM32F410x8/B Electrical characteristics 1. Guaranteed by design. 2. The maximum programming time is measured after 100K erase operations. 3. VPP should only be connected during programming/erasing. Table 49.
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Electrical characteristics STM32F410x8/B In noisy environments, it is recommended to avoid pin exposition to disturbances. The pins showing a middle range robustness are PA14 and PA15. As a consequence, it is recommended to add a serial resistor (1 kΩ maximum) located as close as possible to the MCU pins exposed to noise (connected to tracks longer than 50 mm on PCB).
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STM32F410x8/B 6.3.14 Electrical characteristics Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination.
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Electrical characteristics STM32F410x8/B Functional susceptibility to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures.
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STM32F410x8/B Electrical characteristics Table 55. I/O static characteristics (continued) Symbol VIH Parameter Conditions Min Typ Max FT, TC and NRST I/O input high level voltage(5) 1.7 V≤VDD≤3.6 V 0.7VDD(1) - - 0.17VDD+ 0.
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Electrical characteristics STM32F410x8/B Figure 27.
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STM32F410x8/B Electrical characteristics Table 56.
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Electrical characteristics STM32F410x8/B Table 57.
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STM32F410x8/B Electrical characteristics Figure 28. I/O AC characteristics definition (;7(51$/ 287387 21 &/ WU ,2 RXW WI ,2 RXW 7 0D[LPXP IUHTXHQF\ LV DFKLHYHG LI WU WI 7 DQG LI WKH GXW\ F\FOH LV ZKHQ ORDGHG E\ &/ VSHFLILHG LQ WKH WDEOH ³ , 2 $& FKDUDFWHULVWLFV´ 6.3.17 DL G NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 55).
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Electrical characteristics STM32F410x8/B Figure 29. Recommended NRST pin protection 9'' ([WHUQDO UHVHW FLUFXLW 1567 538 ,QWHUQDO 5HVHW )LOWHU ) 670 ) DL F 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 58. Otherwise the reset is not taken into account by the device. 6.3.18 TIM timer characteristics The parameters given in Table 59 are guaranteed by design.
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STM32F410x8/B 6.3.19 Electrical characteristics Communications interfaces I2C interface characteristics The I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” opendrain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The I2C characteristics are described in Table 60. Refer also to Section 6.3.
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Electrical characteristics STM32F410x8/B 4. The maximum data hold time has only to be met if the interface does not stretch the low period of SCL signal. 5. The minimum width of the spikes filtered by the analog filter is above tSP (max) Figure 30.
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STM32F410x8/B Electrical characteristics Table 62. SCL frequency (fPCLK1= 42 MHz.,VDD = VDD_I2C = 3.3 V)(1)(2) I2C_CCR value fSCL (kHz) RP = 4.7 kΩ 400 0x8019 300 0x8021 200 0x8032 100 0x0096 50 0x012C 20 0x02EE 1. RP = External pull-up resistance, fSCL = I2C speed, 2. For speeds around 200 kHz, the tolerance on the achieved speed is of ±5%. For other speed ranges, the tolerance on the achieved speed ±2%.
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Electrical characteristics STM32F410x8/B FMPI2C characteristics The FMPI2C characteristics are described in Table 63. Refer also to Section 6.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL). Table 63. FMPI2C characteristics(1) Standard mode - fFMPI2CC Fast mode Fast+ mode Parameter Unit Min Max Min Max Min Max 2 - 8 - 17 16(2) - FMPI2CCLK frequency tw(SCLL) SCL clock low time 4.7 - 1.3 - 0.
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STM32F410x8/B Electrical characteristics Figure 31. FMPI2C timing diagram and measurement circuit 9''B, & 9''B, & 53 53 670 )[[ 56 6'$ ,ð& EXV 56 6&/ 67$57 5(3($7(' 67$57 67$57 WVX 67$ 6'$ WI 6'$ WU 6'$ WK 67$ WVX 6'$ WZ 6&/+ WZ 672 67$ 6723 WK 6'$ 6&/ WZ 6&// WU 6&/ WI 6&/ WVX 672 06Y 9 DocID028094 Rev 5 103/142 118 Downloaded from Arrow.com.
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Electrical characteristics STM32F410x8/B SPI interface characteristics Unless otherwise specified, the parameters given in Table 64 for the SPI interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 15, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5VDD Refer to Section 6.3.
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STM32F410x8/B Electrical characteristics Table 64. SPI dynamic characteristics(1) (continued) Symbol Parameter Conditions Min Typ Max Unit ta(SO) Data output access time Slave mode 7 - 21 ns tdis(SO) Data output disable time Slave mode 5 - 12 ns Slave mode (after enable edge), 2.7 V < VDD < 3.6 V - 11 13 ns Slave mode (after enable edge), 1.7 V < VDD < 3.6 V - 11 18.5 ns tv(SO) Data output valid time th(SO) Data output hold time Slave mode (after enable edge), 1.
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Electrical characteristics STM32F410x8/B Figure 33. SPI timing diagram - slave mode and CPHA = 1(1) 166 LQSXW 6&. LQSXW W68 166 &3+$ &32/ &3+$ &32/ WK 166 WF 6&. WZ 6&.+ WZ 6&./ WK 62 WY 62 WD 62 0,62 287387 06% 287 %,7 287 WGLV 62 /6% 287 WK 6, WVX 6, 026, ,1387 WU 6&. WI 6&. 06% ,1 %,7 ,1 /6% ,1 DL E Figure 34. SPI timing diagram - master mode(1) +LJK 166 LQSXW 6&. 2XWSXW &3+$ &32/ 6&. 2XWSXW WF 6&.
PAGE 107
STM32F410x8/B Electrical characteristics I2S interface characteristics Unless otherwise specified, the parameters given in Table 65 for the I2S interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 15, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5VDD Refer to Section 6.3.
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Electrical characteristics STM32F410x8/B Figure 35. I2S slave timing diagram (Philips protocol)(1) &. ,QSXW WF &. &32/ &32/ WZ &.+ WK :6 WZ &./ :6 LQSXW WY 6'B67 WVX :6 6'WUDQVPLW /6% WUDQVPLW 06% WUDQVPLW WVX 6'B65 /6% UHFHLYH 6'UHFHLYH WK 6'B67 %LWQ WUDQVPLW /6% WUDQVPLW WK 6'B65 06% UHFHLYH %LWQ UHFHLYH /6% UHFHLYH DL E 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 36.
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STM32F410x8/B 6.3.20 Electrical characteristics 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 66 are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 15. Table 66. ADC characteristics Symbol VDDA Parameter Power supply VREF+ Positive reference voltage VREF- Negative reference voltage Conditions Min Typ Max 1.7(1) - 3.6 (1) 1.7 - VDDA - 0 - 0.
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Electrical characteristics STM32F410x8/B Table 66. ADC characteristics (continued) Symbol fS(2) Parameter Sampling rate (fADC = 30 MHz, and tS = 3 ADC cycles) Conditions Min Typ Max Unit 12-bit resolution Single ADC - - 2 Msps 12-bit resolution Interleave Dual ADC mode - - 3.
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STM32F410x8/B Electrical characteristics Table 68. ADC accuracy at fADC = 30 MHz(1) Symbol ET Parameter Test conditions Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error fADC = 30 MHz, RAIN < 10 kΩ, VDDA = 2.4 to 3.6 V, VREF = 1.7 to 3.6 V, VDDA −VREF < 1.2 V Typ Max(2) ±2 ±5 ±1.5 ±2.5 ±1.5 ±4 ±1 ±2 ±1.5 ±3 Unit LSB 1. Better performance could be achieved in restricted VDD, frequency and temperature ranges. 2.
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Electrical characteristics Note: STM32F410x8/B ADC accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.
PAGE 113
STM32F410x8/B Electrical characteristics Figure 38. Typical connection diagram using the ADC 670 ) 9'' 5$,1 9$,1 6DPSOH DQG KROG $'& FRQYHUWHU 97 9 5$'& $,1[ &SDUDVLWLF 97 9 ,/ $ ELW FRQYHUWHU & $'& DL 1. Refer to Table 66 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 5 pF). A high Cparasitic value downgrades conversion accuracy.
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Electrical characteristics STM32F410x8/B General PCB design guidelines Power supply decoupling should be performed as shown in Figure 39. The 10 nF capacitors should be ceramic (good quality). They should be placed as close as possible to the chip. Figure 39. Power supply and reference decoupling 670 ) 95() 9''$ ) Q) 95() 9''$ 06Y 9 6.3.21 Temperature sensor characteristics Table 72.
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STM32F410x8/B 6.3.22 Electrical characteristics VBAT monitoring characteristics Table 74. VBAT monitoring characteristics Symbol Parameter Min Typ Max Unit R Resistor bridge for VBAT - 50 - KΩ Q Ratio on VBAT measurement - 4 - - Error on Q –1 - +1 % ADC sampling time when reading the VBAT 1 mV accuracy 5 - - µs Er (1) TS_vbat(2) 1. Guaranteed by design. 2. Shortest sampling time can be determined in the application by multiple iterations. 6.3.
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Electrical characteristics 6.3.24 STM32F410x8/B DAC electrical characteristics Table 77. DAC characteristics Symbol Parameter Conditions Min Typ Max Unit Comments - VDDA Analog supply voltage - 1.7(1) - 3.6 V VREF+ Reference supply voltage - 1.7(1) - 3.
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STM32F410x8/B Electrical characteristics Table 77.
PAGE 118
Electrical characteristics STM32F410x8/B Table 77. DAC characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit Comments - - 6.5 10 µs CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ input code between lowest and highest possible ones. - - - –67 - 40 dB No RLOAD, CLOAD = 50 pF Wakeup time from off state (Setting tWAKEUP(4) the ENx bit in the DAC Control register) PSRR+ (2) Power supply rejection ratio (to VDDA) (static DC measurement) 1. VDDA minimum value of 1.
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STM32F410x8/B 7 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 7.1 WLCSP36 package information Figure 41. WLCSP36 - 36-pin, 2.553 x 2.579 mm, 0.
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Package information STM32F410x8/B Table 79. WLCSP36 - 36-pin, 2.553 x 2.579 mm, 0.4 mm pitch wafer level chip scale package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.525 0.555 0.585 0.0207 0.0219 0.0230 A1 - 0.170 - - 0.0069 - A2 - 0.380 - - 0.0150 - (2) A3 - 0.025 - - 0.0010 - (3) 0.220 0.250 0.280 0.0087 0.0098 0.0110 D 2.518 2.553 2.588 0.1012 0.1026 0.1039 E 2.544 2.579 2.614 0.1050 0.1064 0.1078 e - 0.
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STM32F410x8/B Package information Table 80. WLCSP36 recommended PCB design rules (0.4 mm pitch) Dimension Recommended values Pitch 0.4 mm Dpad 0.225 mm Dsm 0.290 mm typ. (depends on the soldermask registration tolerance) Stencil opening 0.250 mm Stencil thickness 0.100 mm WLCSP36 device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location.
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Package information 7.2 STM32F410x8/B UFQFPN48 package information Figure 44. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package outline 3LQ LGHQWLILHU ODVHU PDUNLQJ DUHD ' $ ( ( 7 GGG $ 6HDWLQJ SODQH E H 'HWDLO < ' ([SRVHG SDG DUHD < ' / & [ SLQ FRUQHU ( 5 W\S 'HWDLO = = $ % B0(B9 1. Drawing is not to scale. 2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life. 3.
PAGE 123
STM32F410x8/B Package information Table 81. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package mechanical data inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. A 0.500 0.550 0.600 0.0197 0.0217 0.0236 A1 0.000 0.020 0.050 0.0000 0.0008 0.0020 D 6.900 7.000 7.100 0.2717 0.2756 0.2795 E 6.900 7.000 7.100 0.2717 0.2756 0.2795 D2 5.500 5.600 5.700 0.2165 0.2205 0.2244 E2 5.500 5.600 5.700 0.2165 0.2205 0.2244 L 0.
PAGE 124
Package information STM32F410x8/B UFQFPN48 device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 46. UFQFPN48 marking example (package top view) 3URGXFW LGHQWLILFDWLRQ 670 ) &%8 'DWH FRGH < :: 3LQ LGHQWLILHU 5HYLVLRQ FRGH 5 06Y 9 1.
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STM32F410x8/B 7.3 Package information LQFP48 package information Figure 47. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline C ! ! ! 3%!4).' 0,!.% # MM '!5'% 0,!.% CCC # + ! $ $ , , $ 0). )$%.4)&)#!4)/. % % % B E "?-%?6 1. Drawing is not to scale. DocID028094 Rev 5 125/142 139 Downloaded from Arrow.com.
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Package information STM32F410x8/B Table 82. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 8.800 9.000 9.200 0.3465 0.3543 0.3622 D1 6.800 7.000 7.200 0.2677 0.2756 0.2835 D3 - 5.500 - - 0.
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STM32F410x8/B Package information Figure 48. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package recommended footprint AI D 1. Dimensions are expressed in millimeters. DocID028094 Rev 5 127/142 139 Downloaded from Arrow.com.
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Package information STM32F410x8/B LQFP48 device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 49. LQFP48 marking example (package top view) 3URGXFW LGHQWLILFDWLRQ 670 ) & 8 'DWH FRGH < :: 5HYLVLRQ FRGH 3LQ LQGHQWLILHU $ 06Y 9 1.
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STM32F410x8/B 7.4 Package information LQFP64 package information Figure 50. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline PP *$8*( 3/$1( F $ $ $ 6($7,1* 3/$1( & $ FFF & ' ' ' . / / 3,1 ,'(17,),&$7,21 ( ( ( E H :B0(B9 1. Drawing is not to scale. DocID028094 Rev 5 129/142 139 Downloaded from Arrow.com.
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Package information STM32F410x8/B Table 83. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D - 12.000 - - 0.4724 - D1 - 10.000 - - 0.3937 - D3 - 7.500 - - 0.2953 - E - 12.000 - - 0.
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STM32F410x8/B Package information LQFP64 device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 52. LQFP64 marking example (package top view) 5HYLVLRQ FRGH 3URGXFW LGHQWLILFDWLRQ 5 670 ) 5%7 'DWH FRGH < :: 3LQ LGHQWLILHU 06Y 9 1.
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Package information 7.5 STM32F410x8/B UFBGA64 package information Figure 53. UFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid array package outline = 6HDWLQJ SODQH GGG = $ $ $ $ $ ( H $ EDOO $ EDOO LGHQWLILHU LQGH[ DUHD ) ; ( $ ) ' ' H < + %27720 9,(: E EDOOV HHH 0 = < ; III 0 = 723 9,(: $ B0(B9 1. Drawing is not to scale. Table 84. UFBGA64 – 64-ball, 5 x 5 mm, 0.
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STM32F410x8/B Package information Table 84. UFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.460 0.530 0.600 0.0181 0.0209 0.0236 F 0.700 0.750 0.800 0.0276 0.0295 0.0315 ddd - - 0.080 - - 0.0031 eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 54.
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Package information STM32F410x8/B UFBGA64 device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 55. UFBGA64 marking example (package top view) 3URGXFW LGHQWLILFDWLRQ ) % 'DWH FRGH
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STM32F410x8/B 7.6 Package information Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 15: General operating conditions on page 53. The maximum chip-junction temperature, TJ max.
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Part numbering 8 STM32F410x8/B Part numbering Table 87.
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STM32F410x8/B Recommendations when using the internal reset OFF Appendix A Recommendations when using the internal reset OFF When the internal reset is OFF, the following integrated features are no longer supported: A.1 • The integrated power-on-reset (POR)/power-down reset (PDR) circuitry is disabled. • The brownout reset (BRO) circuitry must be disabled. By default BOR is OFF. • The embedded programmable voltage detector (PVD) is disabled.
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Application block diagrams Appendix B B.1 STM32F410x8/B Application block diagrams Sensor Hub application example Figure 56. Sensor hub application example 1 $FFHOHURPHWHU *\URVFRSH 670 ) [% :/&63 SDFNDJH [ *3,2V Nവ *3,2 3% 6&/ 3% 6'$ 3$ 7; 3$ 5; 0DJQHWRPHWHU , & 3UHVVXUH $PELHQW OLJKW 3UR[LPLW\ %227 9'' 3'5B21 6:',2 -7$* 6:&/. 6:2 3$ 3$ 3$ 3$ 3% 3% 8$57 166 6&. 63, 0,62 +267 3% 026, 1567 N+] RVFLOODWRU 3& 3$ $'& 7HPSHUDWXUH KXPLGLW\ 3& 06Y
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STM32F410x8/B B.2 Application block diagrams Batch Acquisition Mode (BAM) example Data is transferred through the DMA from interfaces into the internal SRAM while the rest of the MCU is set in low power mode. • Code execution from RAM before switching off the Flash. • Flash is set in power down and flash interface (ART accelerator™) clock is stopped. • The clocks are enabled only for the required interfaces. • MCU core is set in sleep mode (core clock stopped waiting for interrupt).
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Revision history STM32F410x8/B Revision history Table 89. Document revision history Date Revision 28-Sep-2015 1 Initial release. 07-Dec-2015 2 Junction temperature range changed to –40 to + 110 °C for WLCSP49 package. Updated Figure 7: UFQFPN48 pinout.
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STM32F410x8/B Revision history Table 89. Document revision history (continued) Date 06-Mar-2017 04-Apr-2017 Revision Changes 4 Updated: – Features – Section 3.20: Timers and watchdogs – Table 9: STM32F410x8/B pin definitions – Table 21: Typical and maximum current consumption, code with data processing (ART accelerator disabled) running from SRAM - VDD = 1.7 V – Table 22: Typical and maximum current consumption, code with data processing (ART accelerator disabled) running from SRAM - VDD = 3.
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