Datasheet
STM32F405xx, STM32F407xx Electrical characteristics
Doc ID 022152 Rev 2 99/167
5.3.16 I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Ta bl e 4 4 are derived from tests
performed under the conditions summarized in Tabl e 1 1 . All I/Os are CMOS and TTL
compliant.
Table 44. I/O static characteristics
Symbol Parameter Conditions Min Typ Max Unit
V
IL
Input low level voltage
TTL ports
2.7 V
≤ V
DD
≤ 3.6 V
V
SS
–0.3 - 0.8
V
V
IH
(1)
TTa/TC
(2)
I/O input high level voltage 2.0 - V
DD
+0.3
FT
(3)
I/O input high level voltage 2.0 - 5.5
V
IL
Input low level voltage
CMOS ports
1.8 V
≤ V
DD
≤ 3.6 V
V
SS
–0.3 - 0.3V
DD
V
IH
(1)
TTa/TC I/O input high level voltage
0.7V
DD
-3.6
(4)
FT I/O input high level voltage
-5.2
(4)
CMOS ports
2.0 V
≤ V
DD
≤ 3.6 V
-5.5
(4)
V
hys
I/O Schmitt trigger voltage hysteresis
(5)
-200-
mV
IO FT Schmitt trigger voltage
hysteresis
(5)
5% V
DD
(4) -
-
I
lkg
I/O input leakage current
(6)
V
SS
≤ V
IN
≤ V
DD
--±1
µA
I/O FT input leakage current
(6)
V
IN
= 5V - - 3
R
PU
Weak pull-up equivalent
resistor
(7)
All pins
except for
PA10 and
PB12
V
IN
= V
SS
30 40 50
kΩ
PA10 and
PB12
81115
R
PD
Weak pull-down
equivalent resistor
All pins
except for
PA10 and
PB12
V
IN
= V
DD
30 40 50
PA10 and
PB12
81115
C
IO
(8)
I/O pin capacitance 5 pF
1. If V
IH
maximum value cannot be respected, the injection current must be limited externally to I
INJ(PIN)
maximum value.
2. TTa = 3.3 V tolerant I/O directly connected to ADC; TC = standard 3.3 V I/O.
3. FT = 5 V tolerant.
4. With a minimum of 100 mV.
5. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.
6. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins.
7. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
MOS/NMOS contribution
to the series resistance is minimum (~10% order).
8. Guaranteed by design, not tested in production.