Datasheet

Electrical characteristics STM32F405xx, STM32F407xx
90/167 Doc ID 022152 Rev 2
Jitter
(3)
Cycle-to-cycle jitter
System clock
120 MHz
RMS - 25 -
ps
peak
to
peak
- ±150 -
Period Jitter
RMS - 15 -
peak
to
peak
- ±200 -
Main clock output (MCO) for
RMII Ethernet
Cycle to cycle at 50 MHz
on 1000 samples
-32 -
Main clock output (MCO) for MII
Ethernet
Cycle to cycle at 25 MHz
on 1000 samples
-40 -
Bit Time CAN jitter
Cycle to cycle at 1 MHz
on 1000 samples
-330 -
I
DD(PLL)
(4)
PLL power consumption on VDD
VCO freq = 192 MHz
VCO freq = 432 MHz
0.15
0.45
-
0.40
0.75
mA
I
DDA(PLL)
(4)
PLL power consumption on
VDDA
VCO freq = 192 MHz
VCO freq = 432 MHz
0.30
0.55
-
0.40
0.85
mA
1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared
between PLL and PLLI2S.
2. Guaranteed by design, not tested in production.
3. The use of 2 PLLs in parallel could degraded the Jitter up to +30%.
4. Based on characterization, not tested in production.
Table 32. Main PLL characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit
Table 33. PLLI2S (audio PLL) characteristics
(1)
Symbol Parameter Conditions Min Typ Max Unit
f
PLLI2S_IN
PLLI2S input clock
(2)
0.95
(3)
12.10MHz
f
PLLI2S_OUT
PLLI2S multiplier output clock - - 216 MHz
f
VCO_OUT
PLLI2S VCO output 192 - 432 MHz
t
LOCK
PLLI2S lock time
VCO freq = 192 MHz 75 - 200
µs
VCO freq = 432 MHz 100 - 300
Jitter
(4)
Master I2S clock jitter
Cycle to cycle at
12,343 MHz on
48KHz period,
N=432, P=4, R=5
RMS - 90 -
peak
to
peak
- ±280 - ps
Average frequency of
12,343 MHz
N = 432, P = 4, R = 5
on 256 samples
TBD - TBD ps
WS I2S clock jitter
Cycle to cycle at 48 KHz
on 1000 samples
- 400 - ps