Datasheet

STM32F405xx, STM32F407xx Electrical characteristics
Doc ID 022152 Rev 2 71/167
Typical and maximum current consumption
The MCU is placed under the following conditions:
● At startup, all I/O pins are configured as analog inputs by firmware.
● All peripherals are disabled except if it is explicitly mentioned.
● The Flash memory access time is adjusted to f
HCLK
frequency (0 wait state from 0 to
30 MHz, 1 wait state from 30 to 60 MHz, 2 wait states from 60 to 90 MHz, 3 wait states
from 90 to 120 MHz, 4 wait states from 120 to 150 MHz, and 5 wait states from 150 to
168 MHz).
● When the peripherals are enabled HCLK is the system clock, f
PCLK1
= f
HCLK
/4, and
f
PCLK2
= f
HCLK
/2, except is explicitly mentioned.
● The maximum values are obtained for V
DD
= 3.6 V and maximum ambient temperature
(T
A
), and the typical values for T
A
= 25 °C and V
DD
= 3.3 V unless otherwise specified.
Table 17. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART accelerator disabled)
Symbol Parameter Conditions f
HCLK
Typ Max
(1)
Unit
T
A
= 25 °C T
A
= 85 °C T
A
= 105 °C
I
DD
Supply current
in Run mode
External clock
(2)
, all
peripherals enabled
(3)
168 MHz 93 109 117
mA
144 MHz 76 89 96
120 MHz 67 79 86
90 MHz 53 65 73
60 MHz 37 49 56
30 MHz 20 32 39
25 MHz 16 27 35
16 MHz 11 23 30
8 MHz 6 18 25
4 MHz 4 16 23
2 MHz 3 15 22
External clock
(3)
, all
peripherals disabled
168 MHz 46 61 69
144 MHz 40 52 60
120 MHz 37 48 56
90 MHz 30 42 50
60 MHz 22 33 41
30 MHz 12 24 31
25 MHz 10 21 29
16 MHz 7 19 26
8 MHz 4 16 23
4 MHz 3 15 22
2 MHz 2 14 21
1. Based on characterization, tested in production at V
DD
max and f
HCLK
max with peripherals enabled.
2. External clock is 4 MHz and PLL is on when f
HCLK
> 25 MHz.