Datasheet

STM32F405xx, STM32F407xx Electrical characteristics
Doc ID 022152 Rev 2 69/167
5.3.5 Embedded reset and power control block characteristics
The parameters given in Ta bl e 1 6 are derived from tests performed under ambient
temperature and V
DD
supply voltage conditions summarized in Ta bl e 1 1 .
Table 16. Embedded reset and power control block characteristics
Symbol Parameter Conditions Min Typ Max Unit
V
PVD
Programmable voltage
detector level selection
PLS[2:0]=000 (rising
edge)
2.09 2.14 2.19 V
PLS[2:0]=000 (falling
edge)
1.98 2.04 2.08 V
PLS[2:0]=001 (rising
edge)
2.23 2.30 2.37 V
PLS[2:0]=001 (falling
edge)
2.13 2.19 2.25 V
PLS[2:0]=010 (rising
edge)
2.39 2.45 2.51 V
PLS[2:0]=010 (falling
edge)
2.29 2.35 2.39 V
PLS[2:0]=011 (rising
edge)
2.54 2.60 2.65 V
PLS[2:0]=011 (falling
edge)
2.44 2.51 2.56 V
PLS[2:0]=100 (rising
edge)
2.70 2.76 2.82 V
PLS[2:0]=100 (falling
edge)
2.59 2.66 2.71 V
PLS[2:0]=101 (rising
edge)
2.86 2.93 2.99 V
PLS[2:0]=101 (falling
edge)
2.65 2.84 3.02 V
PLS[2:0]=110 (rising
edge)
2.96 3.03 3.10 V
PLS[2:0]=110 (falling
edge)
2.85 2.93 2.99 V
PLS[2:0]=111 (rising
edge)
3.07 3.14 3.21 V
PLS[2:0]=111 (falling
edge)
2.95 3.03 3.09 V
V
PVDhyst
(3)
PVD hysteresis - 100 - mV
V
POR/PDR
Power-on/power-down
reset threshold
Falling edge
TBD
(1)
1.70 TBD V
Rising edge TBD 1.74 TBD V
V
PDRhyst
(3)
PDR hysteresis - 40 - mV