Datasheet

STM32F405xx, STM32F407xx Electrical characteristics
Doc ID 022152 Rev 2 67/167
Table 12. Limitations depending on the operating power supply range
Operating
power
supply
range
ADC
operation
Maximum
Flash
memory
access
frequency
(f
Flashmax
)
Number of wait
states at
maximum CPU
frequency
(1)
I/O operation
Maximum
FSMC_CLK
frequency for
synchronous
accesses
Possible
Flash
memory
operations
V
DD
=1.8 to
2.1 V
(2)
Conversion
time up to
1.2 Msps
16 MHz with
no Flash
memory wait
state
(3)
7
(3)(4)
– Degraded
speed
performance
– No I/O
compensation
up to 30 MHz
8-bit erase
and program
operations
only
V
DD
= 2.1 to
2.4 V
Conversion
time up to
1.2 Msps
18 MHz with
no Flash
memory wait
state
7
(4)
– Degraded
speed
performance
– No I/O
compensation
up to 30 MHz
16-bit erase
and program
operations
V
DD
= 2.4 to
2.7 V
Conversion
time up to
2.4 Msps
24 MHz with
no Flash
memory wait
state
6
(4)
– Degraded
speed
performance
– I/O
compensation
works
up to 48 MHz
16-bit erase
and program
operations
V
DD
= 2.7 to
3.6 V
(5)
Conversion
time up to
2.4 Msps
30 MHz with
no Flash
memory wait
state
5
(4)
– Full-speed
operation
– I/O
compensation
works
–up to
60 MHz
when V
DD
=
3.0 to 3.6 V
–up to
48 MHz
when V
DD
=
2.7 to 3.0 V
32-bit erase
and program
operations
1. The number of wait states can be reduced by reducing the CPU frequency.
2. If an inverted reset signal is applied to PDR_ON, this value can be lowered to 1.7 V when the device operates in a reduced
temperature range (0 to 70 °C).
3. Prefetch is not available. Refer to AN3430 application note for details on how to adjust performance and power.
4. Thanks to the ART accelerator and the 128-bit Flash memory, the number of wait states given here does not impact the
execution speed from Flash memory since the ART accelerator allows to achieve a performance equivalent to 0 wait state
program execution.
5. The voltage range for OTG USB FS can drop down to 2.7 V. However it is degraded between 2.7 and 3 V.