Datasheet

Electrical characteristics STM32F405xx, STM32F407xx
66/167 Doc ID 022152 Rev 2
V
CAP1
When the internal regulator is ON,
V
CAP_1
and V
CAP_2
pins are used to
connect a stabilization capacitor.
When the internal regulator is OFF
(BYPASS_REG connected to V
DD
),
V
CAP_1
and V
CAP_2
must be supplied
from 1.2 V.
1.1 1.3 V
V
CAP2
P
D
Power dissipation at T
A
= 85 °C for
suffix 6 or T
A
= 105 °C for suffix 7
(6)
LQFP64 - 435
mW
LQFP100 - 465
LQFP144 - 500
LQFP176 - 526
UFBGA176 - 513
T
A
Ambient temperature for 6 suffix
version
Maximum power dissipation –40 85
°C
Low power dissipation
(7)
–40 105
Ambient temperature for 7 suffix
version
Maximum power dissipation –40 105
°C
Low power dissipation
(7)
–40 125
T
J Junction temperature range
6 suffix version –40 105
°C
7 suffix version –40 125
1. The average expected gain in power consumption when VOS = 0 compared to VOS = 1 is around 10% for the whole
temperature range, when the system clock frequency is between 30 and 144 MHz.
2. If an inverted reset signal is applied to PDR_ON, this value can be lowered to 1.7 V when the device operates in a reduced
temperature range (0 to 70 °C).
3. When the ADC is used, refer to Table 65: ADC characteristics.
4. If V
REF+
pin is present, it must respect the following condition: V
DDA
-V
REF+
< 1.2 V.
5. It is recommended to power V
DD
and V
DDA
from the same source. A maximum difference of 300 mV between V
DD
and
V
DDA
can be tolerated during power-up and power-down operation.
6. If T
A
is lower, higher P
D
values are allowed as long as T
J
does not exceed T
Jmax
.
7. In low power dissipation state, T
A
can be extended to this range as long as T
J
does not exceed T
Jmax
.
Table 11. General operating conditions (continued)
Symbol Parameter Conditions Min Max Unit