Datasheet

STM32F405xx, STM32F407xx Description
Doc ID 022152 Rev 2 25/167
Regulator OFF
This mode allows to power the device as soon as V
DD
reaches 1.8 V.
● Regulator OFF/internal reset ON
This mode is available only on UFBGA package. It is activated by setting
BYPASS_REG and PDR_ON pins to V
DD
.
The regulator OFF/internal reset ON mode allows to supply externally a 1.2 V voltage
source through V
CAP_1
and V
CAP_2
pins, in addition to V
DD
.
The following conditions must be respected:
–V
DD
should always be higher than V
CAP_1
and V
CAP_2
to avoid current injection
between power domains.
– If the time for V
CAP_1
and V
CAP_2
to reach 1.08 V is faster than the time for V
DD
to
reach 1.8 V (V
DD
/V
DDA
minimum value of 1.7 V is obtained when the device
operates in the 0 to 70 °C temperature range and PDR is disabled), then PA0
should be connected to the NRST pin (see Figure 8). Otherwise, PA0 should be
asserted low externally during POR until V
DD
reaches 1.8 V (see Figure 9).
–If V
CAP_1
and V
CAP_2
go below 1.08 V and V
DD
is higher than 1.7 V, then a reset
must be asserted on PA0 pin.
In regulator OFF/internal reset ON mode, PA0 cannot be used as a GPIO pin since it
allows to reset the part of the 1.2 V logic which is not reset by the NRST pin, when the
internal voltage regulator in off.
● Regulator OFF/internal reset OFF
This mode is available only on UFBGA package. It is activated by setting
BYPASS_REG pin to V
DD
and by applying an inverted reset signal to PDR_ON, and
allows to supply externally a 1.2 V voltage source through V
CAP_1
and V
CAP_2
pins, in
addition to V
DD
.
The following conditions must be respected:
–V
DD
should always be higher than V
CAP_1
and V
CAP_2
to avoid current injection
between power domains.
– PA0 should be kept low to cover both conditions: until V
CAP_1
and V
CAP_2
reach
1.08 V and until V
DD
reaches 1.8 V (see Figure 8).
– NRST should be controlled by an external reset controller to keep the device
under reset when V
DD
is below 1.8 V (see Figure 9).