Datasheet

Description STM32F405xx, STM32F407xx
22/167 Doc ID 022152 Rev 2
pulse width shorter than the Internal APB2 clock period. Up to 140 GPIOs can be connected
to the 16 external interrupt lines.
2.2.12 Clocks and startup
On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The
16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy over the full
temperature range. The application can then select as system clock either the RC oscillator
or an external 4-26 MHz clock source. This clock can be monitored for failure. If a failure is
detected, the system automatically switches back to the internal RC oscillator and a
software interrupt is generated (if enabled). This clock source is input to a PLL thus allowing
to increase the frequency up to 168 MHz. Similarly, full interrupt management of the PLL
clock entry is available when necessary (for example if an indirectly used external oscillator
fails).
Several prescalers allow the configuration of the two AHB buses, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two AHB
buses is 168 MHz while the maximum frequency of the high-speed APB domains is 84 MHz.
The maximum allowed frequency of the low-speed APB domain is 42 MHz.
The devices embed a dedicated PLL (PLLI2S) which allows to achieve audio class
performance. In this case, the I
2
S master clock can generate all standard sampling
frequencies from 8 kHz to 192 kHz.
2.2.13 Boot modes
At startup, boot pins are used to select one out of three boot options:
● Boot from user Flash
● Boot from system memory
● Boot from embedded SRAM
The boot loader is located in system memory. It is used to reprogram the Flash memory by
using USART1 (PA9/PA10), USART3 (PC10/PC11 or PB10/PB11), CAN2 (PB5/PB13), USB
OTG FS in Device mode (PA11/PA12) through DFU (device firmware upgrade).
2.2.14 Power supply schemes
● V
DD
= 1.8 to 3.6 V: external power supply for I/Os and the internal regulator (when
enabled), provided externally through V
DD
pins.
● V
SSA
, V
DDA
= 1.8 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks,
RCs and PLL. V
DDA
and V
SSA
must be connected to V
DD
and V
SS
, respectively.
● V
BAT
= 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup
registers (through power switch) when V
DD
is not present.
Refer to Figure 18: Power supply scheme for more details.
Note: V
DD
/V
DDA
minimum value of 1.7 V is obtained when the device operates in the 0 to 70 °C
temperature range and an inverted reset signal is applied to PDR_ON.