Datasheet
STM32F405xx, STM32F407xx Description
Doc ID 022152 Rev 2 21/167
The DMA can be used with the main peripherals:
● SPI and I
2
S
● I
2
C
● USART
● General-purpose, basic and advanced-control timers TIMx
● DAC
● SDIO
● Camera interface (DCMI)
● ADC.
2.2.9 Flexible static memory controller (FSMC)
The FSMC is embedded in the STM32F405xx and STM32F407xx family. It has four Chip
Select outputs supporting the following modes: PCCard/Compact Flash, SRAM, PSRAM,
NOR Flash and NAND Flash.
Functionality overview:
● Write FIFO
● Maximum FSMC_CLK frequency for synchronous accesses is 60 MHz.
LCD parallel interface
The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to
specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost-
effective graphic applications using LCD modules with embedded controllers or high
performance solutions using external controllers with dedicated acceleration.
2.2.10 Nested vectored interrupt controller (NVIC)
The STM32F405xx and STM32F407xx embed a nested vectored interrupt controller able to
manage 16 priority levels, and handle up to 87 maskable interrupt channels plus the 16
interrupt lines of the Cortex™-M4F.
● Closely coupled NVIC gives low-latency interrupt processing
● Interrupt entry vector table address passed directly to the core
● Allows early processing of interrupts
● Processing of late arriving, higher-priority interrupts
● Support tail chaining
● Processor state automatically saved
● Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimum interrupt
latency.
2.2.11 External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 23 edge-detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a