Datasheet

Application block diagrams STM32F405xx, STM32F407xx
160/167 Doc ID 022152 Rev 2
Figure 88. Audio player solution using PLL, PLLI2S, USB and 1 crystal
Figure 89. Audio PLL (PLLI2S) providing accurate I2S clock
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IN
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I2S CTL
I2S_MCK = 256 × F
SAUDIO
11.2896 MHz for 44.1 kHz
12.2880 MHz for 48.0 kHz
I2S_MCK
PLLI2S
/M
M=1,2,3,..,64
1 MHz
192 to 432 MHz
N=192,194,..,432
I2SCOM_CK
PhaseC
VCO
/N
/R
CLKIN
Phase lock detector
R=2,3,4,5,6,7
I2SD=2,3,4.. 129
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