Datasheet
STM32F405xx, STM32F407xx Electrical characteristics
Doc ID 022152 Rev 2 145/167
Figure 71. SD default mode
5.3.28 RTC characteristics
Table 84. SD / MMC characteristics
(1)
1. TBD stands for “to be defined”.
Symbol Parameter Conditions Min Max Unit
f
PP
Clock frequency in data transfer
mode
C
L
≤ 30 pF TBD TBD MHz
- SDIO_CK/f
PCLK2
frequency ratio - - TBD -
t
W(CKL)
Clock low time, f
PP
= 16 MHz C
L
≤ 30 pF TBD -
ns
t
W(CKH)
Clock high time, f
PP
= 16 MHz C
L
≤ 30 pF TBD -
t
r
Clock rise time C
L
≤ 30 pF - TBD
t
f
Clock fall time C
L
≤ 30 pF - TBD
CMD, D inputs (referenced to CK)
t
ISU
Input setup time C
L
≤ 30 pF TBD -
ns
t
IH
Input hold time C
L
≤ 30 pF TBD -
CMD, D outputs (referenced to CK) in MMC and SD HS mode
t
OV
Output valid time C
L
≤ 30 pF - TBD
ns
t
OH
Output hold time C
L
≤ 30 pF TBD -
CMD, D outputs (referenced to CK) in SD default mode
(2)
2. Refer to SDIO_CLKCR, the SDI clock control register to control the CK output.
t
OVD
Output valid default time C
L
≤ 30 pF - TBD
ns
t
OHD
Output hold default time C
L
≤ 30 pF TBD -
CK
D, CMD
(output)
t
OVD
t
OHD
ai14888
Table 85. RTC characteristics
Symbol Parameter Conditions Min Max Unit
-
f
PCLK1
/RTCCLK
frequency
ratio
Any read/write
operation from/to an
RTC register
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