Datasheet

STM32F405xx, STM32F407xx Electrical characteristics
Doc ID 022152 Rev 2 119/167
t
S
(5)
Sampling time
f
ADC
= 30 MHz 0.100 - 16 µs
3 - 416 1/f
ADC
t
STAB
(5)
Power-up time - 2 3 µs
t
CONV
(5)
Total conversion time (including
sampling time)
f
ADC
= 30 MHz
12-bit resolution
0.416 - 12.95 µs
f
ADC
= 30 MHz
10-bit resolution
0.360 - 12.89 µs
f
ADC
= 30 MHz
8-bit resolution
0.305 - 12.84 µs
f
ADC
= 30 MHz
6-bit resolution
0.250 - 12.79 µs
9 to 492 (t
S
for sampling +n-bit resolution for successive
approximation)
1/f
ADC
f
S
(5)
Sampling rate
(f
ADC
= 30 MHz, and
t
S
= 3 ADC cycles)
12-bit resolution
Single ADC
--2Msps
12-bit resolution
Interleave Dual ADC
mode
- - 3.75 Msps
12-bit resolution
Interleave Triple ADC
mode
--6Msps
I
VREF+
(5)
ADC V
REF
DC current
consumption in conversion
mode
f
ADC
= 30 MHz
3 sampling time
12-bit resolution
- 300 500 µA
f
ADC
= 30 MHz
480 sampling time
12-bit resolution
--TBDµA
I
DDA
(5)
ADC V
DDA
DC current
consumption in conversion
mode
f
ADC
= 30 MHz
3 sampling time
12-bit resolution
-1.61.8
mA
f
ADC
= 30 MHz
480 sampling time
12-bit resolution
--TBD
1. TBD stands for “to be defined”.
2. If an inverted reset signal is applied to PDR_ON, this value can be lowered to 1.7 V when the device operates in a reduced
temperature range (0 to 70 °C).
3. It is recommended to maintain the voltage difference between V
REF+
and V
DDA
below 1.8 V.
4. V
DDA
-V
REF+
< 1.2 V.
5. Based on characterization, not tested in production.
6. V
REF+
is internally connected to V
DDA
and V
REF-
is internally connected to V
SSA
.
7. R
ADC
maximum value is given for V
DD
=1.8 V, and minimum value for V
DD
=3.3 V.
8. For external triggers, a delay of 1/f
PCLK2
must be added to the latency specified in Table 65.
Table 65. ADC characteristics
(1)
(continued)
Symbol Parameter Conditions Min Typ Max Unit