Datasheet

Electrical characteristics STM32F405xx, STM32F407xx
114/167 Doc ID 022152 Rev 2
Figure 42. USB OTG FS timings: definition of data signal rise and fall time
Table 56. USB OTG FS electrical characteristics
(1)
1. Guaranteed by design, not tested in production.
Driver characteristics
Symbol Parameter Conditions Min Max Unit
t
r
Rise time
(2)
2.
Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB
Specification - Chapter 7 (version 2.0).
C
L
= 50 pF 420ns
t
f
Fall time
(2)
C
L
= 50 pF 4 20 ns
t
rfm
Rise/ fall time matching t
r
/t
f
90 110 %
V
CRS
Output signal crossover voltage 1.3 2.0 V
Table 57. USB FS clock timing parameters
(1)(2)
1. Guaranteed by design, not tested in production.
2. TBD stands for “to be defined”.
Parameter Symbol Min Nominal Max Unit
f
HCLK
value to guarantee proper operation of
USB FS interface
- 14.2 MHz
Frequency (first transition) 8-bit ±10% F
START_8BIT
TBD TBD TBD MHz
Frequency (steady state) ±500 ppm F
STEADY
TBD TBD TBD MHz
Duty cycle (first transition) 8-bit ±10% D
START_8BIT
TBD TBD TBD %
Duty cycle (steady state) ±500 ppm D
STEADY
TBD TBD TBD %
Time to reach the steady state frequency and
duty cycle after the first transition
T
STEADY
--TBDms
Clock startup time after the
de-assertion of SuspendM
Peripheral T
START_DEV
--TBD
ms
Host T
START_HOST
---
PHY preparation time after the first transition
of the input clock
T
PREP
---µs
ai14137
t
f
Differen tial
data lines
V
SS
V
CR S
t
r
Crossover
points