Datasheet

STM32F405xx, STM32F407xx Electrical characteristics
Doc ID 022152 Rev 2 111/167
Table 53. I
2
S characteristics
(1)
1. TBD stands for “to be defined”.
Symbol Parameter Conditions Min Max Unit
f
CK
1/t
c(CK)
I
2
S clock frequency
Master TBD TBD
MHz
Slave 0 TBD
t
r(CK)
t
f(CK)
I
2
S clock rise and fall time
capacitive load
C
L
= 50 pF
- TBD
ns
t
v(WS)
(2)
2. Based on design simulation and/or characterization results, not tested in production.
WS valid time Master TBD -
t
h(WS)
(2)
WS hold time Master TBD -
t
su(WS)
(2)
WS setup time Slave TBD -
t
h(WS)
(2)
WS hold time Slave TBD -
t
w(CKH)
(2)
t
w(CKL)
(2)
CK high and low time
Master f
PCLK
= TBD,
presc = TBD
TBD -
t
su(SD_MR)
(2)
t
su(SD_SR)
(2)
Data input setup time
Master receiver
Slave receiver
TBD
TBD
-
t
h(SD_MR)
(2)(3)
t
h(SD_SR)
(2)(3)
3. Depends on f
PCLK
. For example, if f
PCLK
=8 MHz, then T
PCLK
= 1/f
PLCLK
=125 ns.
Data input hold time
Master receiver
Slave receiver
TBD
TBD
-
t
h(SD_MR)
(2)
t
h(SD_SR)
(2)
Data input hold time
Master f
PCLK
= TBD
Slave f
PCLK
= TBD
TBD
TBD
-
t
v(SD_ST)
(2)(3)
Data output valid time
Slave transmitter
(after enable edge)
- TBD
f
PCLK
= TBD - TBD
t
h(SD_ST)
(2)
Data output hold time
Slave transmitter
(after enable edge)
TBD -
t
v(SD_MT)
(2)(3)
Data output valid time
Master transmitter
(after enable edge)
- TBD
f
PCLK
= TBD
TBD TBD
t
h(SD_MT)
(2)
Data output hold time
Master transmitter
(after enable edge)
TBD -