Datasheet

Electrical characteristics STM32F405xx, STM32F407xx
106/167 Doc ID 022152 Rev 2
Table 50. I
2
C characteristics
Symbol Parameter
Standard mode I
2
C
(1)
1.
Guaranteed by design, not tested in production.
Fast mode I
2
C
(1)(2)
2. f
PCLK1
must be at least 2 MHz to achieve standard mode I
2
C frequencies. It must be at least 4 MHz to
achieve fast mode I
2
C frequencies, and a multiple of 10 MHz to reach the 400 kHz maximum I
2
C fast mode
clock.
Unit
Min Max Min Max
t
w(SCLL)
SCL clock low time 4.7 - 1.3 -
µs
t
w(SCLH)
SCL clock high time 4.0 - 0.6 -
t
su(SDA)
SDA setup time 250 - 100 -
ns
t
h(SDA)
SDA data hold time 0
(3)
3.
The maximum hold time of the Start condition has only to be met if the interface does not stretch the low
period of SCL signal.
-0
(4)
4.
The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL.
900
(3)
t
r(SDA)
t
r(SCL)
SDA and SCL rise time - 1000 20 + 0.1C
b
300
t
f(SDA)
t
f(SCL)
SDA and SCL fall time - 300 - 300
t
h(STA)
Start condition hold time 4.0 - 0.6 -
µs
t
su(STA)
Repeated Start condition
setup time
4.7 - 0.6 -
t
su(STO)
Stop condition setup time 4.0 - 0.6 - μs
t
w(STO:STA)
Stop to Start condition time
(bus free)
4.7 - 1.3 - μs
C
b
Capacitive load for each bus
line
- 400 - 400 pF