Datasheet

STM32F405xx, STM32F407xx Electrical characteristics
Doc ID 022152 Rev 2 105/167
5.3.19 Communications interfaces
I
2
C interface characteristics
Unless otherwise specified, the parameters given in Ta bl e 5 0 are derived from tests
performed under the ambient temperature, f
PCLK1
frequency and V
DD
supply voltage
conditions summarized in Ta bl e 1 1.
The STM32F405xx and STM32F407xx
I
2
C interface meets the requirements of the
standard I
2
C communication protocol with the following restrictions: the I/O pins SDA and
SCL are mapped to are not “true” open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and V
DD
is disabled, but is still present.
The I
2
C characteristics are described in Ta ble 5 0 . Refer also to Section 5.3.16: I/O port
characteristics
for more details on the input/output alternate function characteristics (SDA
and SCL)
.
Table 49. Characteristics of TIMx connected to the APB2 domain
(1)
1. TIMx is used as a general term to refer to the TIM1, TIM8, TIM9, TIM10, and TIM11 timers.
Symbol Parameter Conditions Min Max Unit
t
res(TIM)
Timer resolution time
AHB/APB2
prescaler distinct
from 1, f
TIMxCLK
=
168 MHz
1-
t
TIMxCLK
5.95 - ns
AHB/APB2
prescaler = 1,
f
TIMxCLK
= 84 MHz
1-
t
TIMxCLK
11.9 - ns
f
EXT
Timer external clock
frequency on CH1 to CH4
f
TIMxCLK
= 168 MHz
APB2 = 84 MHz
0
f
TIMxCLK
/2
MHz
084MHz
Res
TIM
Timer resolution - 16 bit
t
COUNTER
16-bit counter clock
period when internal clock
is selected
1 65536
t
TIMxCLK
t
MAX_COUNT
Maximum possible count - 32768
t
TIMxCLK