Datasheet

STM32F405xx, STM32F407xx Electrical characteristics
Doc ID 022152 Rev 2 103/167
5.3.17 NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, R
PU
(see Ta bl e 4 4 ).
Unless otherwise specified, the parameters given in Ta bl e 4 7 are derived from tests
performed under the ambient temperature and V
DD
supply voltage conditions summarized
in Ta bl e 11 .
Figure 35. Recommended NRST pin protection
2. The reset network protects the device against parasitic resets.
3. The user must ensure that the level on the NRST pin can go below the V
IL(NRST)
max level specified in
Table 47. Otherwise the reset is not taken into account by the device.
Table 47. NRST pin characteristics
Symbol Parameter Conditions Min Typ Max Unit
V
IL(NRST)
(1)
1. Guaranteed by design, not tested in production.
NRST Input low level voltage –0.5 - 0.8
V
V
IH(NRST)
(1)
NRST Input high level voltage 2 - V
DD
+0.5
V
hys(NRST)
NRST Schmitt trigger voltage
hysteresis
- 200 - mV
R
PU
Weak pull-up equivalent resistor
(2)
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution
to the series resistance must be minimum (~10% order).
V
IN
= V
SS
30 40 50 kΩ
V
F(NRST)
(1)
NRST Input filtered pulse - - 100 ns
V
NF(NRST)
(1)
NRST Input not filtered pulse V
DD
> 2.7 V 300 - - ns
T
NRST_OUT
Generated reset pulse duration
Internal
Reset source
20 - - µs
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