Datasheet

Electrical characteristics STM32F405xx, STM32F407xx
100/167 Doc ID 022152 Rev 2
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters.
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source ±20 mA (with a relaxed V
OL
/V
OH
).
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 5.2. In particular:
● The sum of the currents sourced by all the I/Os on V
DD,
plus the maximum Run
consumption of the MCU sourced on V
DD,
cannot exceed the absolute maximum rating
I
VDD
(see Ta bl e 9 ).
● The sum of the currents sunk by all the I/Os on V
SS
plus the maximum Run
consumption of the MCU sunk on V
SS
cannot exceed the absolute maximum rating
I
VSS
(see Ta bl e 9 ).
Output voltage levels
Unless otherwise specified, the parameters given in Ta bl e 4 5 are derived from tests
performed under ambient temperature and V
DD
supply voltage conditions summarized in
Table 1 1 . All I/Os are CMOS and TTL compliant.
Table 45. Output voltage characteristics
(1)
1. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited
amount of current (3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited: the speed
should not exceed 2 MHz with a maximum load of 30 pF and these I/Os must not be used as a current
source (e.g. to drive an LED).
Symbol Parameter Conditions Min Max Unit
V
OL
(2)
2. The I
IO
current sunk by the device must always respect the absolute maximum rating specified in Table 9
and the sum of I
IO
(I/O ports and control pins) must not exceed I
VSS
.
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
TTL port
I
IO
= +8 mA
2.7 V < V
DD
< 3.6 V
-0.4
V
V
OH
(3)
3. The I
IO
current sourced by the device must always respect the absolute maximum rating specified in
Table 9 and the sum of I
IO
(I/O ports and control pins) must not exceed I
VDD
.
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
V
DD
–0.4 -
V
OL
(2)
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
CMOS port
I
IO
=+ 8mA
2.7 V < V
DD
< 3.6 V
-0.4
V
V
OH
(3)
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
2.4 -
V
OL
(2)(4)
4. Based on characterization data, not tested in production.
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
I
IO
= +20 mA
2.7 V < V
DD
< 3.6 V
-1.3
V
V
OH
(3)(4)
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
V
DD
–1.3 -
V
OL
(2)(4)
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
I
IO
= +6 mA
2 V < V
DD
< 2.7 V
-0.4
V
V
OH
(3)(4)
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
V
DD
–0.4 -