Datasheet

ManualsBrandsST ManualsEmbedded Processors & ControllersMicrocontroller 32bit 1MB LQFP

January 2012 Doc ID 022152 Rev 2 1/167

STM32F405xx

STM32F407xx

ARM Cortex-M4 32b MCU+FPU, 210DMIPS, up to 1MB Flash/192+4KB RAM,

USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera

Features

■ Core: ARM 32-bit Cortex™-M4 CPU with FPU,

Adaptive real-time accelerator (ART

Accelerator™) allowing 0-wait state execution

from Flash memory, frequency up to 168 MHz,

memory protection unit, 210 DMIPS/

1.25 DMIPS/MHz (Dhrystone 2.1), and DSP

instructions

■ Memories

– Up to 1 Mbyte of Flash memory

– Up to 192+4 Kbytes of SRAM including 64-

Kbyte of CCM (core coupled memory) data

RAM

– Flexible static memory controller

supporting Compact Flash, SRAM,

PSRAM, NOR and NAND memories

■ LCD parallel interface, 8080/6800 modes

■ Clock, reset and supply management

– 1.8 V to 3.6 V application supply and I/Os

– POR, PDR, PVD and BOR

– 4-to-26 MHz crystal oscillator

– Internal 16 MHz factory-trimmed RC (1%

accuracy)

– 32 kHz oscillator for RTC with calibration

– Internal 32 kHz RC with calibration

● Low power

– Sleep, Stop and Standby modes

–V

BAT

supply for RTC, 20×32 bit backup

registers + optional 4 KB backup SRAM

■ 3×12-bit, 2.4 MSPS A/D converters: up to 24

channels and 7.2 MSPS in triple interleaved

mode

■ 2×12-bit D/A converters

■ General-purpose DMA: 16-stream DMA

controller with FIFOs and burst support

■ Up to 17 timers: up to twelve 16-bit and two 32-

bit timers up to 168 MHz, each with up to 4

IC/OC/PWM or pulse counter and quadrature

(incremental) encoder input

■ Debug mode

– Serial wire debug (SWD) & JTAG interfaces

– Cortex-M4 Embedded Trace Macrocell™

1. The WLCSP90 package will soon be available.

■

Up to 140 I/O ports with interrupt capability

– Up to 136 fast I/Os up to 84 MHz

– Up to 138 5 V-tolerant I/Os

■ Up to 15 communication interfaces

– Up to 3 × I

C interfaces (SMBus/PMBus)

– Up to 4 USARTs/2 UARTs (10.5 Mbit/s,

ISO 7816 interface, LIN, IrDA, modem

control)

– Up to 3 SPIs (37.5 Mbits/s), 2 with muxed

full-duplex I

S to achieve audio class

accuracy via internal audio PLL or external

clock

– 2 × CAN interfaces (2.0B Active)

– SDIO interface

■ Advanced connectivity

– USB 2.0 full-speed device/host/OTG

controller with on-chip PHY

– USB 2.0 high-speed/full-speed

device/host/OTG controller with dedicated

DMA, on-chip full-speed PHY and ULPI

– 10/100 Ethernet MAC with dedicated DMA:

supports IEEE 1588v2 hardware, MII/RMII

■ 8- to 14-bit parallel camera interface up to

54 Mbytes/s

■ True random number generator

■ CRC calculation unit

■ 96-bit unique ID

■ RTC: subsecond accuracy, hardware calendar

Table 1. Device summary

Reference Part number

STM32F405xx STM32F405RG, STM32F405VG, STM32F405ZG

STM32F407xx

STM32F407VG, STM32F407IG, STM32F407ZG,

STM32F407VE, STM32F407ZE, STM32F407IE

LQFP64 (10 × 10 mm)

LQFP100 (14 × 14 mm)

LQFP144 (20 × 20 mm)

FBGA

UFBGA176

(10 × 10 mm)

LQFP176 (24 × 24 mm)

WLCSP90

www.st.com

Summary of content (167 pages)

PAGE 1
STM32F405xx STM32F407xx ARM Cortex-M4 32b MCU+FPU, 210DMIPS, up to 1MB Flash/192+4KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera Features ■ FBGA Core: ARM 32-bit Cortex™-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 168 MHz, memory protection unit, 210 DMIPS/ 1.25 DMIPS/MHz (Dhrystone 2.
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Contents STM32F405xx, STM32F407xx Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2/167 2.1 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2.
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STM32F405xx, STM32F407xx Contents 2.2.30 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . 34 2.2.31 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.2.32 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.2.33 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . 35 2.2.34 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . .
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Contents 6 7 STM32F405xx, STM32F407xx 5.3.13 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 5.3.14 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 97 5.3.15 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 5.3.16 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 5.3.17 NRST pin characteristics . . . . . .
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STM32F405xx, STM32F407xx List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46.
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List of tables Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94.
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STM32F405xx, STM32F407xx List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39.
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List of figures Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83. Figure 84.
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STM32F405xx, STM32F407xx Figure 87. Figure 88. Figure 89. Figure 90. Figure 91. Figure 92. Figure 93. Figure 94. List of figures Complete audio player solution 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Audio player solution using PLL, PLLI2S, USB and 1 crystal . . . . . . . . . . . . . . . . . . . . . . 160 Audio PLL (PLLI2S) providing accurate I2S clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Introduction 1 STM32F405xx, STM32F407xx Introduction This datasheet provides the description of the STM32F405xx and STM32F407xx lines of microcontrollers. For more details on the whole STMicroelectronics STM32™ family, please refer to Section 2.1: Full compatibility throughout the family. The STM32F405xx and STM32F407xx datasheet should be read in conjunction with the STM32F4xx reference manual.
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STM32F405xx, STM32F407xx 2 Description Description The STM32F405xx and STM32F407xx family is based on the high-performance ARM® Cortex™-M4 32-bit RISC core operating at a frequency of up to 168 MHz. The Cortex-M4 core features a Floating point unit (FPU) single precision which supports all ARM singleprecision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security.
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Table 2.
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STM32F405xx and STM32F407xx: features and peripheral counts (continued) Peripherals STM32F405RG STM32F405ZG STM32F407Vx STM32F407Zx STM32F407Ix Ambient temperatures: –40 to +85 °C /–40 to +105 °C Operating temperatures Package STM32F405VG Junction temperature: –40 to + 125 °C LQFP64 LQFP100 LQFP144 LQFP100 1. VDD/VDDA minimum value of 1.7 V is obtained when the device operates in the 0 to 70 °C temperature range and PDR is disabled. LQFP144 UFBGA176 LQFP176 STM32F405xx, STM32F407xx Table 2.
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Description 2.1 STM32F405xx, STM32F407xx Full compatibility throughout the family The STM32F405xx and STM32F407xx are part of the STM32F4 family. They are fully pinto-pin, software and feature compatible with the STM32F2xx devices, allowing the user to try different memory densities, peripherals, and performances (FPU, higher frequency) for a greater degree of freedom during the development cycle. The STM32F405xx and STM32F407xx devices maintain a close compatibility with the whole STM32F10xxx family.
PAGE 15
STM32F405xx, STM32F407xx Figure 2. Description Compatible board design STM32F10xx/STM32F2xx/STM32F4xx for LQFP100 package 633 633 633 633 6$$ 6 33 4WO Ω RESISTORS CONNECTED TO 6$$ 633 6 33 FOR THE 34- & XX 6 33 FOR THE 34- & XX 6 33 6 $$ OR .# FOR THE 34- & XX Figure 3.
PAGE 16
Description STM32F405xx, STM32F407xx Figure 4. Compatible board design between STM32F2xx and STM32F4xx for LQFP176 package )NVERTED RESET SIGNAL 0$2?/. 6$$ 6 33 4WO Ω RESISTORS CONNECTED TO 6 33 6 $$ OR .
PAGE 17
STM32F405xx, STM32F407xx Description 2.2 Device overview Figure 5. STM32F40x block diagram %XTERNAL MEMORY CONTROLLER &3-# ##- DATA 2!- +" $ "53 $-! &)&/ 53" /4' (3 3TREAMS $-! 2.
PAGE 18
Description STM32F405xx, STM32F407xx from TIMxCLK up to 84 MHz. 2. The camera interface is available only on STM32F407xxdevices. 2.2.1 ARM® Cortex™-M4F core with embedded Flash and SRAM The ARM Cortex-M4F processor is the latest generation of ARM processors for embedded systems.
PAGE 19
STM32F405xx, STM32F407xx 2.2.4 Description Embedded Flash memory The STM32F40x devices embed a Flash memory of 256 Kbytes, 512 Kbytes, 768 Kbytes or 1 Mbytes available for storing programs and data. 2.2.5 CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity.
PAGE 20
Description Multi-AHB matrix 3 3 3 53"?(3?- -!# 53" /4' %THERNET (3 %4(%2.%4?- $-!?0 $-!?-%- $-!?-%- 3 '0 $-! 3 3 - )#/$% - $#/$% !##%, 3 $-!?0) ) BUS 3 '0 $-! 3 BUS !2#ORTEX - +BYTE ##- DATA 2!- $ BUS Figure 6. STM32F405xx, STM32F407xx &LASH MEMORY - 32! +BYTE - 32! +BYTE !(" PERIPH !(" PERIPH - - - &3-# 3TATIC -EM#TL !0" !0" "US MATRIX 3 AI 2.2.
PAGE 21
STM32F405xx, STM32F407xx Description The DMA can be used with the main peripherals: 2.2.9 ● SPI and I2S ● I2C ● USART ● General-purpose, basic and advanced-control timers TIMx ● DAC ● SDIO ● Camera interface (DCMI) ● ADC. Flexible static memory controller (FSMC) The FSMC is embedded in the STM32F405xx and STM32F407xx family. It has four Chip Select outputs supporting the following modes: PCCard/Compact Flash, SRAM, PSRAM, NOR Flash and NAND Flash.
PAGE 22
Description STM32F405xx, STM32F407xx pulse width shorter than the Internal APB2 clock period. Up to 140 GPIOs can be connected to the 16 external interrupt lines. 2.2.12 Clocks and startup On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The 16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy over the full temperature range. The application can then select as system clock either the RC oscillator or an external 4-26 MHz clock source.
PAGE 23
STM32F405xx, STM32F407xx 2.2.15 Description Power supply supervisor The power supply supervisor is enabled by holding PDR_ON high. The device has an integrated power-on reset (POR) / power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry. At power-on, BOR is always active, and ensures proper operation starting from 1.8 V. After the 1.
PAGE 24
Description STM32F405xx, STM32F407xx VDD minimum value is 1.8 V. VDD/VDDA minimum value of 1.7 V is obtained when the device operates in the 0 to 70 °C temperature range and PDR is disabled.
PAGE 25
STM32F405xx, STM32F407xx Description Regulator OFF This mode allows to power the device as soon as VDD reaches 1.8 V. ● Regulator OFF/internal reset ON This mode is available only on UFBGA package. It is activated by setting BYPASS_REG and PDR_ON pins to VDD. The regulator OFF/internal reset ON mode allows to supply externally a 1.2 V voltage source through VCAP_1 and VCAP_2 pins, in addition to VDD.
PAGE 26
Description STM32F405xx, STM32F407xx Figure 8. Startup in regulator OFF: slow VDD slope - power-down reset risen after VCAP_1/VCAP_2 stabilization 6$$ 0$2 6 6#!0? 6 #!0? 6 6 TIME 0! TIED TO .234 .234 TIME AI C 1. This figure is valid both whatever the internal reset mode (on or off). Figure 9. Startup in regulator OFF mode: fast VDD slope - power-down reset risen before VCAP_1/VCAP_2 stabilization 6$$ 0$2 6 6#!0? 6 #!0? 6 6 TIME 0! ASSERTED EXTERNALLY .
PAGE 27
STM32F405xx, STM32F407xx Description It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation. Two alarm registers are used to generate an alarm at a specific time and calendar fields can be independently masked for alarm comparison.
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Description STM32F405xx, STM32F407xx Standby mode, the SRAM and register contents are lost except for registers in the backup domain and the backup SRAM when selected. The device exits the Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin, or an RTC alarm / wakeup / tamper /time stamp event occurs. Note: When in Standby mode, only an RTC alarm/event or an external reset can wake up the device provided VDD is supplied by an external battery. 2.2.
PAGE 29
STM32F405xx, STM32F407xx Table 3.
PAGE 30
Description STM32F405xx, STM32F407xx General-purpose timers (TIMx) There are ten synchronizable general-purpose timers embedded in the STM32F40x devices (see Table 3 for differences). ● TIM2, TIM3, TIM4, TIM5 The STM32F40x include 4 full-featured general-purpose timers: TIM2, TIM5, TIM3, and TIM4.The TIM2 and TIM5 timers are based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. The TIM3 and TIM4 timers are based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler.
PAGE 31
STM32F405xx, STM32F407xx Description SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard downcounter. It features: 2.2.21 ● A 24-bit downcounter ● Autoreload capability ● Maskable system interrupt generation when the counter reaches 0 ● Programmable clock source. Inter-integrated circuit interface (I²C) Up to three I²C bus interfaces can operate in multimaster and slave modes. They can support the Standard- and Fast-modes.
PAGE 32
Description Table 4. STM32F405xx, STM32F407xx USART feature comparison USART Standard Modem SPI LIN irDA name features (RTS/CTS) master Smartcard (ISO 7816) Max. baud rate Max. baud rate in Mbit/s in Mbit/s (oversampling (oversampling by 16) by 8) APB mapping USART1 X X X X X X 5.25 10.5 APB2 (max. 84 MHz) USART2 X X X X X X 2.62 5.25 APB1 (max. 42 MHz) USART3 X X X X X X 2.62 5.25 APB1 (max. 42 MHz) UART4 X - X - X - 2.62 5.25 APB1 (max.
PAGE 33
STM32F405xx, STM32F407xx 2.2.25 Description Audio PLL (PLLI2S) The devices feature an additional dedicated PLL for audio I2S application. It allows to achieve error-free I2S sampling clock accuracy without compromising on the CPU performance, while using USB peripherals. The PLLI2S configuration can be modified to manage an I2S sample rate change without disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces.
PAGE 34
Description STM32F405xx, STM32F407xx The STM32F407xx includes the following features: 2.2.
PAGE 35
STM32F405xx, STM32F407xx Description The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG 1.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The major features are: 2.2.
PAGE 36
Description 2.2.34 STM32F405xx, STM32F407xx Analog-to-digital converters (ADCs) Three 12-bit analog-to-digital converters are embedded and each ADC shares up to 16 external channels, performing conversions in the single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs. Additional logic functions embedded in the ADC interface allow: ● Simultaneous sample and hold ● Interleaved sample and hold The ADC can be served by the DMA controller.
PAGE 37
STM32F405xx, STM32F407xx Description Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. 2.2.
PAGE 38
Pinouts and pin description 3 STM32F405xx, STM32F407xx Pinouts and pin description 6$$ 633 0" 0" "//4 0" 0" 0" 0" 0" 0$ 0# 0# 0# 0! 0! Figure 10.
PAGE 39
STM32F405xx, STM32F407xx Pinouts and pin description 6$$ 0$2?/. 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! Figure 11.
PAGE 40
Pinouts and pin description STM32F405xx, STM32F407xx 6$$ 0$2?/. 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0' 6$$ 633 0' 0' 0' 0' 0' 0' 0$ 0$ 6$$ 633 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! Figure 12.
PAGE 41
STM32F405xx, STM32F407xx Pinouts and pin description 0$2?/. 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0' 6$$ 633 0' 0' 0' 0' 0' 0' 0$ 0$ 6$$ 633 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! 6$$ 633 0) 0) 0) 0) 0) 0) 6 $$ Figure 13.
PAGE 42
Pinouts and pin description STM32F405xx, STM32F407xx Figure 14. STM32F40x UFBGA176 ballout ! 0% 0% 0% 0% 0" 0" 0' 0' 0" 0" 0$ 0# 0! 0! 0! " 0% 0% 0% 0" 0" 0" 0' 0' 0' 0' 0$ 0$ 0# 0# 0! # 6"!4 0) 0) 0) 6$$ 0$2?/.
PAGE 43
STM32F405xx, STM32F407xx Table 5.
PAGE 44
Pinouts and pin description LQFP144 UFBGA176 LQFP176 (function after reset)(1) Pin type I / O structure - 1 1 A2 1 PE2 I/O FT TRACECLK/ FSMC_A23 / ETH_MII_TXD3 / EVENTOUT - 2 2 A1 2 PE3 I/O FT TRACED0/FSMC_A19 / EVENTOUT - 3 3 B1 3 PE4 I/O FT TRACED1/FSMC_A20 / DCMI_D4/ EVENTOUT - 4 4 B2 4 PE5 I/O FT TRACED2 / FSMC_A21 / TIM9_CH1 / DCMI_D6 / EVENTOUT - 5 5 B3 5 PE6 I/O FT TRACED3 / FSMC_A22 / TIM9_CH2 / DCMI_D7 / EVENTOUT 1 6 6 C1 6 VBAT S - - -
PAGE 45
STM32F405xx, STM32F407xx Notes STM32F40x pin and ball definitions (continued) I / O structure Table 6.
PAGE 46
Pinouts and pin description N3 (function after reset)(1) 40 PA0-WKUP (PA0) Pin type Pin name LQFP176 14 23 34 UFBGA176 LQFP144 LQFP100 LQFP64 Pin number I/O Notes STM32F40x pin and ball definitions (continued) I / O structure Table 6.
PAGE 47
STM32F405xx, STM32F407xx Notes STM32F40x pin and ball definitions (continued) I / O structure Table 6.
PAGE 48
Pinouts and pin description LQFP64 LQFP100 LQFP144 UFBGA176 LQFP176 Pin name (function after reset)(1) - - 62 N9 72 VDD Pin type Pin number Notes STM32F40x pin and ball definitions (continued) I / O structure Table 6.
PAGE 49
STM32F405xx, STM32F407xx I/O FT TIM5_CH3 / DCMI_D3/ EVENTOUT FT SPI2_NSS / I2S2_WS / I2C2_SMBA/ USART3_CK/ TIM1_BKIN / CAN2_RX / OTG_HS_ULPI_D5/ ETH_RMII_TXD0 / ETH_MII_TXD0/ OTG_HS_ID/ EVENTOUT FT SPI2_SCK / I2S2_CK / USART3_CTS/ TIM1_CH1N /CAN2_TX / OTG_HS_ULPI_D6 / ETH_RMII_TXD1 / ETH_MII_TXD1/ EVENTOUT FT SPI2_MISO/ TIM1_CH2N / TIM12_CH1 / OTG_HS_DM/ USART3_RTS / TIM8_CH2N/I2S2ext_SD/ EVENTOUT LQFP144 LQFP176 LQFP100 Pin name LQFP64 UFBGA176 Pin number - - - K12 89 PH12 - - - H1
PAGE 50
Pinouts and pin description I/O FT FSMC_A18/TIM4_CH2/ EVENTOUT - LQFP176 UFBGA176 LQFP144 LQFP100 LQFP64 Pin number 60 82 M15 101 - Pin name (function after reset)(1) PD13 - - 83 102 VSS S - - 84 J13 103 VDD S Notes I / O structure STM32F40x pin and ball definitions (continued) Pin type Table 6.
PAGE 51
STM32F405xx, STM32F407xx Pin name (function after reset)(1) Pin type LQFP176 UFBGA176 LQFP144 LQFP100 LQFP64 Pin number Notes STM32F40x pin and ball definitions (continued) I / O structure Table 6.
PAGE 52
Pinouts and pin description I / O structure 49 76 109 A14 137 PA14 (JTCK-SWCLK) I/O FT JTCK-SWCLK/ EVENTOUT 50 77 110 A13 138 PA15 (JTDI) I/O FT JTDI/ SPI3_NSS/ I2S3_WS/TIM2_CH1_ETR / SPI1_NSS / EVENTOUT FT SPI3_SCK / I2S3_CK/ UART4_TX/SDIO_D2 / DCMI_D8 / USART3_TX/ EVENTOUT FT UART4_RX/ SPI3_MISO / SDIO_D3 / DCMI_D4/USART3_RX / I2S3ext_SD/ EVENTOUT UFBGA176 LQFP144 LQFP100 LQFP64 Pin number 51 78 111 B14 139 52 79 112 B13 140 53 80 113 A12 141 Pin name PC10 PC11 I/O I/O Notes
PAGE 53
STM32F405xx, STM32F407xx I/O FT FSMC_NCE4_1/ FSMC_NE3/ EVENTOUT LQFP176 - UFBGA176 LQFP100 - LQFP144 LQFP64 Pin number 125 B10 153 Pin name (function after reset)(1) PG10 Notes I / O structure STM32F40x pin and ball definitions (continued) Pin type Table 6.
PAGE 54
Pinouts and pin description Pin name (function after reset)(1) Pin type LQFP176 UFBGA176 LQFP144 LQFP100 LQFP64 Pin number 59 93 137 B5 165 PB7 I/O FT 60 94 138 D6 166 BOOT0 I B 61 95 139 A5 167 62 96 140 B4 168 PB8 I/O Notes STM32F40x pin and ball definitions (continued) I / O structure Table 6.
PAGE 55
STM32F405xx, STM32F407xx Pinouts and pin description 5. If the device is delivered in an UFBGA176 and the BYPASS_REG pin is set to VDD (Regulator off/internal reset ON mode), then PA0 is used as an internal Reset (active low).
PAGE 56
Alternate function mapping AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 USART2_CTS UART4_TX ETH_MII_CRS UART4_RX ETH_MII _RX_CLK ETH_RMII _REF_CLK EVENTOUT ETH_MDIO EVENTOUT Port SYS PA0 TIM1/2 TIM3/4/5 TIM8/9/10/11 TIM2_CH1 TIM2_ETR TIM 5_CH1 TIM8_ETR PA1 TIM2_CH2 TIM5_CH2 PA2 TIM2_CH3 TIM5_CH3 TIM9_CH1 USART2_RTS PA3 TIM2_CH4 TIM5_CH4 TIM9_CH2 AF9 CAN1/CAN2/ OTG_FS/ OTG_HS TIM12/13/14 U
PAGE 57
Alternate function mapping (continued) AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 Port PB15 SYS TIM1/2 RTC_50Hz TIM1_CH3N TIM3/4/5 TIM8/9/10/11 SPI2_MOSI I2S2_SD TIM8_CH3N AF9 AF10 CAN1/CAN2/ OTG_FS/ OTG_HS TIM12/13/14 AF12 AF13 ETH FSMC/SDIO/ OTG_FS DCMI TIM12_CH2 PC0 AF014 OTG_HS_DP EVENTOUT ETH_MDC PC2 SPI2_MISO PC3 SPI2_MOSI I2S2_SD I2S2ext_SD OTG_HS_ULPI_DIR OTG_HS_ULPI_NXT PC4 PC5
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Alternate function mapping (continued) AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 Port SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 AF9 AF10 CAN1/CAN2/ OTG_FS/ OTG_HS TIM12/13/14 AF11 AF12 AF13 ETH FSMC/SDIO/ OTG_FS DCMI AF014 AF15 PD15 TIM4_CH4 FSMC_D1 PE0 TIM4_ETR FSMC_NBL0 DCMI_D2 EVENTOUT FSMC_BLN1 DCMI_D3 EVENTOUT PE1 ETH _MII_TXD3 EVENTOUT PE2 TRACECLK FSMC_A23 PE3 TRACED0 EVENTOUT FSMC_
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Alternate function mapping (continued) AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 Port SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 AF9 AF10 CAN1/CAN2/ OTG_FS/ OTG_HS TIM12/13/14 AF11 AF12 AF13 ETH FSMC/SDIO/ OTG_FS DCMI AF014 AF15 PG0 FSMC_A10 EVENTOUT PG1 FSMC_A11 EVENTOUT PG2 FSMC_A12 EVENTOUT PG3 FSMC_A13 EVENTOUT PG4 FSMC_A14 EVENTOUT PG5 FSMC_A15 EVENTOUT PG6 FSMC_INT2 EVENTOUT FSMC_IN
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Alternate function mapping (continued) AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 Port SYS TIM1/2 TIM3/4/5 PH15 PI0 TIM8/9/10/11 AF9 AF10 CAN1/CAN2/ OTG_FS/ OTG_HS TIM12/13/14 AF11 AF12 AF13 ETH FSMC/SDIO/ OTG_FS DCMI TIM8_CH3N SPI2_NSS I2S2_WS SPI2_SCK I2S2_CK TIM5_CH4 PI1 I2S2ext_SD AF014 AF15 DCMI_D11 EVENTOUT DCMI_D13 EVENTOUT DCMI_D8 EVENTOUT PI2 TIM8_CH4 SPI2_MISO PI3 TIM8_ETR S
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STM32F405xx, STM32F407xx 4 Memory map Memory map The memory map is shown in Figure 15. Figure 15. Memory map 2ESERVED !(" 2ESERVED !(" 2ESERVED !(" X&&&& &&&& X% X$&&& &&&& 2ESERVED -BYTE BLOCK #ORTEX - gS INTERNAL PERIPHERALS !(" 2ESERVED -BYTE BLOCK .
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Electrical characteristics STM32F405xx, STM32F407xx 5 Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range).
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STM32F405xx, STM32F407xx 5.1.6 Electrical characteristics Power supply scheme Figure 18. Power supply scheme 6"!4 /54 '0 ) /S ). § & )/ ,OGIC +ERNEL LOGIC #05 DIGITAL 2!- 6#!0? 6#!0? 6$$ § N& § & ,EVEL SHIFTER 6"!4 TO 6 6$$ "ACKUP CIRCUITRY /3# + 24# 7AKEUP LOGIC "ACKUP REGISTERS BACKUP 2!- 0O WER SWI TCH 6OLTAGE REGULATOR 633 &LASH MEMORY "90!33?2%' 0$2?/.
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Electrical characteristics 5.1.7 STM32F405xx, STM32F407xx Current consumption measurement Figure 19. Current consumption measurement scheme IDD_VBAT VBAT IDD VDD VDDA ai14126 5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 8: Voltage characteristics, Table 9: Current characteristics, and Table 10: Thermal characteristics may cause permanent damage to the device.
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STM32F405xx, STM32F407xx Table 9. Electrical characteristics Current characteristics Symbol Ratings Max.
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Electrical characteristics Table 11. STM32F405xx, STM32F407xx General operating conditions (continued) Symbol Parameter VCAP1 When the internal regulator is ON, VCAP_1 and VCAP_2 pins are used to connect a stabilization capacitor. When the internal regulator is OFF (BYPASS_REG connected to VDD), VCAP_1 and VCAP_2 must be supplied from 1.2 V. VCAP2 PD Conditions Power dissipation at TA = 85 °C for suffix 6 or TA = 105 °C for suffix 7(6) Min Max Unit 1.1 1.
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STM32F405xx, STM32F407xx Table 12. Limitations depending on the operating power supply range Operating power supply range ADC operation Maximum Flash memory access frequency (fFlashmax) VDD =1.8 to 2.1 V(2) Conversion time up to 1.2 Msps 16 MHz with no Flash memory wait state(3) VDD = 2.1 to 2.4 V Conversion time up to 1.2 Msps 18 MHz with no Flash memory wait state Conversion time up to 2.4 Msps 24 MHz with no Flash memory wait state VDD = 2.4 to 2.7 V VDD = 2.7 to 3.
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Electrical characteristics 5.3.2 STM32F405xx, STM32F407xx VCAP1/VCAP2 external capacitor Stabilization for the main regulator is achieved by connecting an external capacitor CEXT to the VCAP1/VCAP2 pins. CEXT is specified in Table 13. Figure 20. External capacitor CEXT C ESR R Leak MS19044V1 1. Legend: ESR is the equivalent series resistance. Table 13. 5.3.3 VCAP1/VCAP2 operating conditions Symbol Parameter Conditions CEXT Capacitance of external capacitor 2.
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STM32F405xx, STM32F407xx 5.3.5 Electrical characteristics Embedded reset and power control block characteristics The parameters given in Table 16 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 11. Table 16.
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Electrical characteristics Table 16. STM32F405xx, STM32F407xx Embedded reset and power control block characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit Brownout level 1 threshold Falling edge 2.13 2.19 2.24 V VBOR1 Rising edge 2.23 2.29 2.33 V Brownout level 2 threshold Falling edge 2.44 2.50 2.56 V VBOR2 Rising edge 2.53 2.59 2.63 V Brownout level 3 threshold Falling edge 2.75 2.83 2.88 V VBOR3 Rising edge 2.85 2.92 2.
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STM32F405xx, STM32F407xx Electrical characteristics Typical and maximum current consumption The MCU is placed under the following conditions: Table 17. ● At startup, all I/O pins are configured as analog inputs by firmware. ● All peripherals are disabled except if it is explicitly mentioned.
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Electrical characteristics STM32F405xx, STM32F407xx 3. When analog peripheral blocks such as (ADCs, DACs, HSE, LSE, HSI,LSI) are on, an additional power consumption should be considered. Table 18.
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STM32F405xx, STM32F407xx Electrical characteristics Figure 21. Typical current consumption vs temperature, Run mode, code with data processing running from Flash (ART accelerator ON) or RAM, and peripherals OFF )$$ 25. M! # # # # # # #05 &REQUENCY -(Z -3 6 Figure 22.
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Electrical characteristics STM32F405xx, STM32F407xx Figure 23. Typical current consumption vs temperature, Run mode, code with data processing running from Flash (ART accelerator OFF) or RAM, and peripherals OFF )$$ 25. M! # # # # # # #05 &REQUENCY -(Z -3 6 Figure 24.
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STM32F405xx, STM32F407xx Table 19.
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Electrical characteristics Table 20. STM32F405xx, STM32F407xx Typical and maximum current consumptions in Stop mode Typ Symbol Parameter Supply current in Stop mode with main regulator in Run mode IDD_STOP TA = 25 °C TA = 25 °C TA = 85 °C TA = 105 °C Flash in Stop mode, low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) 0.60 1.20 11.00 20.
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STM32F405xx, STM32F407xx Electrical characteristics Typical and maximum current consumptions in VBAT mode(1) Table 22. Typ Symbol Parameter Max TA = 25 °C Conditions TA = 85 °C VBAT = VBAT= VBAT = 1.8 V 2.4 V 3.3 V Backup SRAM ON, low-speed oscillator and RTC ON Backup Backup SRAM OFF, low-speed IDD_VBAT domain supply oscillator and RTC ON current Backup SRAM ON, RTC OFF Backup SRAM OFF, RTC OFF TA = 105 °C VBAT = 3.6 V 1.29 1.42 1.68 TBD(2) TBD(2) 0.62 0.73 0.96 TBD(2) TBD(2) 0.
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Electrical characteristics STM32F405xx, STM32F407xx Figure 26. Typical VBAT current consumption (LSE and RTC ON/backup RAM ON) 6 5 IVBAT in (μA) 4 1.65V 1.8V 2V 3 2.4V 2.7V 3V 2 3.3V 3.6V 1 0 0 10 20 30 40 50 60 70 80 90 100 Temperature in (°C) -3 6 I/O system current consumption The current consumption of the I/O system has two components: static and dynamic.
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STM32F405xx, STM32F407xx Electrical characteristics voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin: I SW = V DD × f SW × C where ISW is the current sunk by a switching I/O to charge/discharge the capacitive load VDD is the MCU supply voltage fSW is the I/O switching frequency C is the total capacitance seen by the I/O pin: C = CINT+ CEXT The test pin is configured in push-pull output mode and is toggled by software at a fixe
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Electrical characteristics Table 23. Symbol STM32F405xx, STM32F407xx Switching output I/O current consumption Parameter Conditions(1) I/O toggling frequency (fSW) Typ 2 MHz 0.02 8 MHz 0.14 25 MHz 0.51 50 MHz 0.86 60 MHz 1.30 2 MHz 0.10 8 MHz 0.38 25 MHz 1.18 50 MHz 2.47 60 MHz 2.86 2 MHz 0.17 8 MHz 0.66 25 MHz 1.70 50 MHz 2.65 60 MHz 3.48 2 MHz 0.23 8 MHz 0.95 25 MHz 3.20 50 MHz 4.69 60 MHz 8.06 2 MHz 0.30 8 MHz 1.22 25 MHz 3.90 50 MHz 8.
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STM32F405xx, STM32F407xx Electrical characteristics On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 24. The MCU is placed under the following conditions: ● At startup, all I/O pins are configured as analog pins by firmware. ● All peripherals are disabled unless otherwise mentioned ● The code is running from Flash memory and the Flash memory access time is equal to 5 wait states at 168 MHz.
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Electrical characteristics Table 24. STM32F405xx, STM32F407xx Peripheral current consumption (continued) Peripheral(1) AHB3 168 MHz 144 MHz FSMC 2.18 1.67 TIM2 0.80 0.61 TIM3 0.58 0.44 TIM4 0.62 0.48 TIM5 0.79 0.61 TIM6 0.15 0.11 TIM7 0.16 0.12 TIM12 0.33 0.26 TIM13 0.27 0.21 TIM14 0.27 0.21 PWR 0.04 0.03 USART2 0.17 0.13 USART3 0.17 0.13 UART4 0.17 0.13 UART5 0.17 0.13 I2C1 0.17 0.13 I2C2 0.18 0.13 APB1 I2C3 0.18 0.13 SPI2/I2S2 (2) 0.17/0.
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STM32F405xx, STM32F407xx Table 24. Electrical characteristics Peripheral current consumption (continued) Peripheral(1) 168 MHz 144 MHz SDIO 0.64 0.54 TIM1 1.47 1.14 TIM8 1.58 1.22 TIM9 0.68 0.54 TIM10 0.45 0.36 TIM11 0.47 0.38 (5) 2.20 2.10 ADC2(5) 2.04 1.93 (5) 2.10 2.00 SPI1 0.14 0.12 USART1 0.34 0.27 USART6 0.34 0.28 APB2 ADC1 ADC3 Unit mA 1. HSE oscillator with 4 MHz crysta) and PLL are on. 2.
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Electrical characteristics 5.3.8 STM32F405xx, STM32F407xx External clock source characteristics High-speed external user clock generated from an external source The characteristics given in Table 26 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 11. Table 26.
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STM32F405xx, STM32F407xx Electrical characteristics Figure 27. High-speed external clock source AC timing diagram VHSEH 90% VHSEL 10% tr(HSE) tf(HSE) t tW(HSE) tW(HSE) THSE External clock source fHSE_ext OSC _IN IL STM32F ai17528 Figure 28.
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Electrical characteristics Table 28. Symbol STM32F405xx, STM32F407xx HSE 4-26 MHz oscillator characteristics(1) (2) Min Typ Max Unit Oscillator frequency 4 - 26 MHz RF Feedback resistor - 200 - kΩ C Recommended load capacitance versus equivalent serial resistance of the crystal (RS)(3) RS = 30 Ω - 15 - pF i2 HSE driving current VDD = 3.
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STM32F405xx, STM32F407xx Table 29. Electrical characteristics LSE oscillator characteristics (fLSE = 32.768 kHz) (1)(2) Symbol Parameter Conditions RF Feedback resistor C(3) Recommended load capacitance versus equivalent serial resistance of the crystal (RS)(4) I2 LSE driving current gm Oscillator Transconductance tSU(LSE)(5) Min Typ Max Unit - TBD - MΩ RS = 30 kΩ - - TBD pF VDD = 3.3 V, VIN = VSS - - TBD µA TBD - - µA/V - TBD - s startup time VDD is stabilized 1.
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Electrical characteristics 5.3.9 STM32F405xx, STM32F407xx Internal clock source characteristics The parameters given in Table 30 and Table 31 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 11. High-speed internal (HSI) RC oscillator Low-speed internal (LSI) RC oscillator Table 30. Symbol HSI oscillator characteristics (1) Parameter Conditions Min Typ Max Unit - 16 - MHz - - 1 % TA = –40 to 105 °C –8 - 4.
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STM32F405xx, STM32F407xx Electrical characteristics Figure 31. ACCLSI versus temperature MAX AVG MIN .ORMALIZED DEVIATI ON 4EMPERAT URE # -3 6 5.3.10 PLL characteristics The parameters given in Table 32 and Table 33 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 11. Table 32.
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Electrical characteristics Table 32.
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STM32F405xx, STM32F407xx Table 33. Electrical characteristics PLLI2S (audio PLL) characteristics(1) (continued) Symbol Parameter Conditions IDD(PLLI2S)(5) PLLI2S power consumption on VDD VCO freq = 192 MHz VCO freq = 432 MHz IDDA(PLLI2S)(5) PLLI2S power consumption on VDDA VCO freq = 192 MHz VCO freq = 432 MHz Min Typ Max Unit 0.15 0.45 - 0.40 0.75 mA - 0.40 0.85 mA 0.30 0.55 1. TBD stands for “to be defined”. 2.
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Electrical characteristics 5.3.11 STM32F405xx, STM32F407xx PLL spread spectrum clock generation (SSCG) characteristics The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic interferences (see Table 40: EMI characteristics). It is available only on the main PLL. Table 34. SSCG parameters constraint Symbol Parameter Min Typ Max(1) Unit fMod Modulation frequency - - 10 KHz md Peak modulation depth 0.25 - 2 % - 215 - MODEPER * INCSTEP - −1 1.
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STM32F405xx, STM32F407xx Electrical characteristics Figure 32 and Figure 33 show the main PLL output clock waveforms in center spread and down spread modes, where: F0 is fPLL_OUT nominal. Tmode is the modulation period. md is the modulation depth. Figure 32. PLL output clock waveforms in center spread mode &REQUENCY 0,,?/54 MD & MD TMODE 4IME TMODE AI Figure 33. PLL output clock waveforms in down spread mode &REQUENCY 0,,?/54 & MD TMODE 4IME TMODE AI 5.3.
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Electrical characteristics STM32F405xx, STM32F407xx 1. TBD stands for “to be defined”. Table 36.
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STM32F405xx, STM32F407xx Electrical characteristics Flash memory programming with VPP(1) Table 37. Min(1) Typ Max(2) Double word programming - 16 100(3) tERASE16KB Sector (16 KB) erase time - TBD - tERASE64KB Sector (64 KB) erase time - TBD - - TBD - - 6.8 - 2.7 - 3.
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Electrical characteristics STM32F405xx, STM32F407xx A device reset allows normal operations to be resumed. The test results are given in Table 39. They are based on the EMS levels and classes defined in application note AN1709. Table 39. EMS characteristics Symbol Parameter Conditions Level/ Class VFESD VDD = 3.
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STM32F405xx, STM32F407xx Electrical characteristics Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application, executing EEMBC® code, is running. This emission test is compliant with SAE IEC61967-2 standard which specifies the test board and the pin loading. Table 40. Symbol EMI characteristics Parameter Max vs. [fHSE/fCPU] Monitored frequency band Conditions Unit 25/168 MHz VDD = 3.
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Electrical characteristics STM32F405xx, STM32F407xx Static latchup Two complementary static tests are required on six parts to assess the latchup performance: ● A supply overvoltage is applied to each power supply pin ● A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78A IC latchup standard. Table 42. Electrical sensitivities Symbol LU 5.3.
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STM32F405xx, STM32F407xx 5.3.16 Electrical characteristics I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 44 are derived from tests performed under the conditions summarized in Table 11. All I/Os are CMOS and TTL compliant. Table 44. I/O static characteristics Symbol VIL VIH(1) VIL Parameter Conditions Typ Max VSS–0.3 - 0.8 2.0 - VDD+0.3 2.0 - 5.5 VSS–0.3 - 0.3VDD - 3.6(4) - 5.2(4) - 5.
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Electrical characteristics STM32F405xx, STM32F407xx All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. Output driving current The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or source ±20 mA (with a relaxed VOL/VOH). In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 5.
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STM32F405xx, STM32F407xx Electrical characteristics Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 34 and Table 46, respectively. Unless otherwise specified, the parameters given in Table 46 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 11. Table 46.
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Electrical characteristics Table 46. OSPEEDRy [1:0] bit value(1) STM32F405xx, STM32F407xx I/O AC characteristics(1)(2)(3) (continued) Symbol Parameter Conditions Fmax(IO)out Maximum frequency(4) 11 - tf(IO)out Output high to low level fall time tr(IO)out Output low to high level rise time tEXTIpw Pulse width of external signals detected by the EXTI controller Min Typ Max CL = 30 pF, VDD > 2.70 V - - 100(5) CL = 30 pF, VDD > 1.8 V - - 50(5) CL = 10 pF, VDD > 2.
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STM32F405xx, STM32F407xx 5.3.17 Electrical characteristics NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 44). Unless otherwise specified, the parameters given in Table 47 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 11. Table 47.
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Electrical characteristics 5.3.18 STM32F405xx, STM32F407xx TIM timer characteristics The parameters given in Table 48 and Table 49 are guaranteed by design. Refer to Section 5.3.16: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 48.
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STM32F405xx, STM32F407xx Table 49.
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Electrical characteristics Table 50. STM32F405xx, STM32F407xx I2C characteristics Standard mode I2C(1) Symbol Fast mode I2C(1)(2) Parameter Unit Min Max Min Max tw(SCLL) SCL clock low time 4.7 - 1.3 - tw(SCLH) SCL clock high time 4.0 - 0.6 - tsu(SDA) SDA setup time 250 - 100 - - (4) µs (3) 900(3) th(SDA) SDA data hold time tr(SDA) tr(SCL) SDA and SCL rise time - 1000 20 + 0.
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STM32F405xx, STM32F407xx Electrical characteristics Figure 36. I2C bus AC waveforms and measurement circuit 6$$ KΩ 6$$ KΩ Ω Ω )£# BUS 34- &XX 3$! 3#, 3 4!24 2%0%!4%$ 3 4!24 3 4!24 TSU 34! 3$! TF 3$! TR 3$! TH 34! TSU 3$! TW 3#,, 3#, TW 3#,( TR 3#, TW 34/ 34! 3 4/0 TH 3$! TSU 34/ TF 3#, AI B 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. Table 51. SCL frequency (fPCLK1= 42 MHz.,VDD = 3.3 V)(1)(2) I2C_CCR value fSCL (kHz) RP = 4.
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Electrical characteristics STM32F405xx, STM32F407xx I2S - SPI interface characteristics Unless otherwise specified, the parameters given in Table 52 for SPI or in Table 53 for I2S are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 11. Refer to Section 5.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S). Table 52.
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STM32F405xx, STM32F407xx Electrical characteristics Figure 37. SPI timing diagram - slave mode and CPHA = 0 NSS input tc(SCK) th(NSS) SCK Input tSU(NSS) CPHA= 0 CPOL=0 tw(SCKH) tw(SCKL) CPHA= 0 CPOL=1 tv(SO) ta(SO) MISO OUT P UT tr(SCK) tf(SCK) th(SO) MS B O UT BI T6 OUT tdis(SO) LSB OUT tsu(SI) MOSI I NPUT B I T1 IN M SB IN LSB IN th(SI) ai14134c Figure 38.
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Electrical characteristics STM32F405xx, STM32F407xx Figure 39. SPI timing diagram - master mode(1) High NSS input SCK Input SCK Input tc(SCK) CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=0 CPHA=1 CPOL=1 tsu(MI) MISO INP UT tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) MS BIN BI T6 IN LSB IN th(MI) MOSI OUTUT M SB OUT B I T1 OUT tv(MO) LSB OUT th(MO) ai14136 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
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STM32F405xx, STM32F407xx Table 53.
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Electrical characteristics STM32F405xx, STM32F407xx Figure 40. I2S slave timing diagram (Philips protocol)(1) CK Input tc(CK) CPOL = 0 CPOL = 1 tw(CKH) th(WS) tw(CKL) WS input tv(SD_ST) tsu(WS) SDtransmit LSB transmit(2) MSB transmit Bitn transmit tsu(SD_SR) LSB receive(2) SDreceive th(SD_ST) LSB transmit th(SD_SR) MSB receive Bitn receive LSB receive ai14881b 1. Measurement points are done at CMOS levels: 0.3 × VDD and 0.7 × VDD. 2.
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STM32F405xx, STM32F407xx Electrical characteristics USB OTG FS characteristics This interface is present in both the USB OTG HS and USB OTG FS controllers. Table 54. USB OTG FS startup time Symbol tSTARTUP(1) Parameter USB OTG FS transceiver startup time Max Unit 1 µs 1. Guaranteed by design, not tested in production. Table 55. USB OTG FS DC electrical characteristics Symbol VDD Input levels Parameter Conditions USB OTG FS operating voltage Min.(1) Typ. Max.(1) Unit 3.0(2) - 3.
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Electrical characteristics STM32F405xx, STM32F407xx Figure 42. USB OTG FS timings: definition of data signal rise and fall time Crossover points Differen tial data lines VCRS VS S Table 56. tr tf ai14137 USB OTG FS electrical characteristics(1) Driver characteristics Symbol tr tf trfm VCRS Parameter Rise time(2) Fall time(2) Conditions Min Max Unit CL = 50 pF 4 20 ns CL = 50 pF 4 20 ns tr/tf 90 110 % 1.3 2.0 V Rise/ fall time matching Output signal crossover voltage 1.
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STM32F405xx, STM32F407xx Electrical characteristics USB HS characteristics Table 58 shows the USB HS operating voltage. Table 58. USB HS DC electrical characteristics Symbol Input level Parameter VDD Ethernet operating voltage Min.(1) Max.(1) Unit 2.7 3.6 V Nominal Max 1. All the voltages are measured from the local ground potential. Table 59.
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Electrical characteristics Table 60. STM32F405xx, STM32F407xx ULPI timing Value(1) Parameter Symbol Control in (ULPI_DIR) setup time tSC Control in (ULPI_NXT) setup time Unit Min. Max. - 2.0 - 1.5 - Control in (ULPI_DIR, ULPI_NXT) hold time tHC Data in setup time tSD - 2.0 Data in hold time tHD 0 - Control out (ULPI_STP) setup time and hold time tDC - 9.2 Data out available from clock rising edge tDD - 10.7 Min.(1) Max.(1) Unit 2.7 3.6 V ns 1. VDD = 2.7 V to 3.
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STM32F405xx, STM32F407xx Electrical characteristics Table 63 gives the list of Ethernet MAC signals for the RMII and Figure 45 shows the corresponding timing diagram. Figure 45. Ethernet RMII timing diagram RMII_REF_CLK td(TXEN) td(TXD) RMII_TX_EN RMII_TXD[1:0] tsu(RXD) tsu(CRS) tih(RXD) tih(CRS) RMII_RXD[1:0] RMII_CRS_DV ai15667 Table 63.
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Electrical characteristics Table 64. STM32F405xx, STM32F407xx Dynamics characteristics: Ethernet MAC signals for MII(1) Symbol Rating Min Typ Max Unit tsu(RXD) Receive data setup time TBD TBD TBD ns tih(RXD) Receive data hold time TBD TBD TBD ns tsu(DV) Data valid setup time TBD TBD TBD ns tih(DV) Data valid hold time TBD TBD TBD ns tsu(ER) Error setup time TBD TBD TBD ns tih(ER) Error hold time TBD TBD TBD ns td(TXEN) Transmit enable valid delay time 13.4 15.
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STM32F405xx, STM32F407xx Table 65. Symbol ADC characteristics(1) (continued) Parameter tS(5) Sampling time tSTAB(5) Power-up time tCONV(5) Electrical characteristics Conditions Min Typ Max Unit fADC = 30 MHz 0.100 - 16 µs 3 - 416 1/fADC - 2 3 µs fADC = 30 MHz 12-bit resolution 0.416 - 12.95 µs fADC = 30 MHz 10-bit resolution 0.360 - 12.89 µs fADC = 30 MHz 8-bit resolution 0.305 - 12.84 µs fADC = 30 MHz 6-bit resolution 0.250 - 12.
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Electrical characteristics STM32F405xx, STM32F407xx Equation 1: RAIN max formula R AIN ( k – 0.5 ) - – R ADC = ------------------------------------------------------------N+2 f ADC × C ADC × ln ( 2 ) The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of sampling periods defined in the ADC_SMPR1 register. a Table 66.
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STM32F405xx, STM32F407xx Electrical characteristics Figure 47. ADC accuracy characteristics 6 6 ; ,3")$%!, 2%& OR $$! DEPENDING ON PACKAGE = %' %4 %/ %, %$ , 3")$%!, 633! 6$$! AI C 1. See also Table 66. 2. Example of an actual transfer curve. 3. Ideal transfer curve. 4. End point correlation line. 5. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.
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Electrical characteristics STM32F405xx, STM32F407xx General PCB design guidelines Power supply decoupling should be performed as shown in Figure 49 or Figure 50, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 49.
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STM32F405xx, STM32F407xx Electrical characteristics 5.3.21 Temperature sensor characteristics Table 67. TS characteristics Symbol Parameter TL(1) Avg_Slope (1) V25(1) tSTART(2) TS_temp (3)(2) Min Typ Max Unit VSENSE linearity with temperature - ±1 ±2 °C Average slope - 2.5 mV/°C Voltage at 25 °C - 0.76 V Startup time - 6 10 µs 10 - - µs ADC sampling time when reading the temperature (1 °C accuracy) 1. Based on characterization, not tested in production. 2.
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Electrical characteristics STM32F405xx, STM32F407xx 5.3.24 DAC electrical characteristics Table 70. DAC characteristics Symbol Parameter Min Typ Max Unit Comments VDDA Analog supply voltage 1.8(1) - 3.6 V VREF+ Reference supply voltage 1.8(1) - 3.
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STM32F405xx, STM32F407xx Table 70. Symbol INL(3) Offset(3) Gain error(3) Electrical characteristics DAC characteristics (continued) Parameter Min Typ Max Unit - - ±1 LSB Given for the DAC in 10-bit configuration. - - ±4 LSB Given for the DAC in 12-bit configuration. - - ±10 mV Given for the DAC in 12-bit configuration - - ±3 LSB Given for the DAC in 10-bit at VREF+ = 3.6 V - - ±12 LSB Given for the DAC in 12-bit at VREF+ = 3.6 V - - ±0.
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Electrical characteristics STM32F405xx, STM32F407xx Figure 51. 12-bit buffered /non-buffered DAC Buffered/Non-buffered DAC Buffer(1) R LOAD DACx_OUT 12-bit digital to analog converter C LOAD ai17157 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. 5.3.
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STM32F405xx, STM32F407xx Electrical characteristics Figure 52. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms TW .% &3-#?.% TV ./%?.% T W ./% T H .%?./% &3-#?./% &3-#?.7% TV !?.% &3-#?!; = T H !?./% !DDRESS TV ",?.% T H ",?./% &3-#?.",; = T H $ATA?.% T SU $ATA?./% TH $ATA?./% T SU $ATA?.% $ATA &3-#?$; = T V .!$6?.% TW .!$6 &3-#?.!$6 AI C 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Table 71.
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Electrical characteristics STM32F405xx, STM32F407xx Figure 53. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms tw(NE) FSMC_NEx FSMC_NOE tv(NWE_NE) tw(NWE) t h(NE_NWE) FSMC_NWE tv(A_NE) FSMC_A[25:0] th(A_NWE) Address tv(BL_NE) FSMC_NBL[1:0] th(BL_NWE) NBL tv(Data_NE) th(Data_NWE) Data FSMC_D[15:0] t v(NADV_NE) tw(NADV) FSMC_NADV(1) ai14990 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Table 72.
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STM32F405xx, STM32F407xx Electrical characteristics Figure 54. Asynchronous multiplexed PSRAM/NOR read waveforms tw(NE) FSMC_NE tv(NOE_NE) t h(NE_NOE) FSMC_NOE t w(NOE) FSMC_NWE tv(A_NE) FSMC_A[25:16] t h(A_NOE) Address tv(BL_NE) th(BL_NOE) FSMC_NBL[1:0] NBL th(Data_NE) tsu(Data_NE) t v(A_NE) tsu(Data_NOE) Address FSMC_AD[15:0] t v(NADV_NE) th(Data_NOE) Data th(AD_NADV) tw(NADV) FSMC_NADV ai14892b Table 73.
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Electrical characteristics STM32F405xx, STM32F407xx Figure 55. Asynchronous multiplexed PSRAM/NOR write waveforms tw(NE) FSMC_NEx FSMC_NOE tv(NWE_NE) tw(NWE) t h(NE_NWE) FSMC_NWE tv(A_NE) FSMC_A[25:16] th(A_NWE) Address tv(BL_NE) th(BL_NWE) FSMC_NBL[1:0] NBL t v(A_NE) t v(Data_NADV) Address FSMC_AD[15:0] t v(NADV_NE) th(Data_NWE) Data th(AD_NADV) tw(NADV) FSMC_NADV ai14891B Table 74.
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STM32F405xx, STM32F407xx Electrical characteristics Synchronous waveforms and timings Figure 56 through Figure 59 represent synchronous waveforms and Table 76 through Table 78 provide the corresponding timings.
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Electrical characteristics Table 75. STM32F405xx, STM32F407xx Synchronous multiplexed NOR/PSRAM read timings(1)(2) Symbol tw(CLK) Parameter FSMC_CLK period Max Unit 2THCLK - ns td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..
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STM32F405xx, STM32F407xx Electrical characteristics Figure 57. Synchronous multiplexed PSRAM write timings "53452. TW #,+ TW #,+ &3-#?#,+ $ATA LATENCY TD #,+, .%X, TD #,+, .%X( &3-#?.%X TD #,+, .!$6, TD #,+, .!$6( &3-#?.!$6 TD #,+, !6 TD #,+, !)6 &3-#?!; = TD #,+, .7%, TD #,+, .7%( &3-#?.7% TD #,+, !$)6 TD #,+, $ATA TD #,+, $ATA TD #,+, !$6 !$; = &3-#?!$; = $ $ &3-#?.7!)4 7!)4#&' B 7!)40/, B TSU .7!)46 #,+( TH #,+( .7!)46 TD #,+, .",( &3-#?.
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Electrical characteristics STM32F405xx, STM32F407xx Figure 58. Synchronous non-multiplexed NOR/PSRAM read timings "53452. TW #,+ TW #,+ &3-#?#,+ TD #,+, .%X, TD #,+, .%X( $ATA LATENCY &3-#?.%X TD #,+, .!$6, TD #,+, .!$6( &3-#?.!$6 TD #,+, !)6 TD #,+, !6 &3-#?!; = TD #,+, ./%, TD #,+, ./%( &3-#?./% TSU $6 #,+( TH #,+( $6 TSU $6 #,+( &3-#?$; = $ TSU .7!)46 #,+( TH #,+( $6 $ TH #,+( .7!)46 &3-#?.7!)4 7!)4#&' B 7!)40/, B TSU .7!)46 #,+( T H #,+( .7!)46 &3-#?.
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STM32F405xx, STM32F407xx Electrical characteristics Figure 59. Synchronous non-multiplexed PSRAM write timings TW #,+ "53452. TW #,+ &3-#?#,+ TD #,+, .%X, TD #,+, .%X( $ATA LATENCY &3-#?.%X TD #,+, .!$6, TD #,+, .!$6( &3-#?.!$6 TD #,+, !6 TD #,+, !)6 &3-#?!; = TD #,+, .7%, TD #,+, .7%( &3-#?.7% TD #,+, $ATA &3-#?$; = TD #,+, $ATA $ $ &3-#?.7!)4 7!)4#&' B 7!)40/, B TSU .7!)46 #,+( TD #,+, .",( TH #,+( .7!)46 &3-#?.", AI G Table 78.
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Electrical characteristics STM32F405xx, STM32F407xx PC Card/CompactFlash controller waveforms and timings Figure 60 through Figure 65 represent synchronous waveforms, and Table 79 and Table 80 provide the corresponding timings. The results shown in this table are obtained with the following FSMC configuration: ● COM.FSMC_SetupTime = 0x04; ● COM.FSMC_WaitSetupTime = 0x07; ● COM.FSMC_HoldSetupTime = 0x04; ● COM.FSMC_HiZSetupTime = 0x00; ● ATT.FSMC_SetupTime = 0x04; ● ATT.
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STM32F405xx, STM32F407xx Electrical characteristics Figure 61.
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Electrical characteristics STM32F405xx, STM32F407xx Figure 62. PC Card/CompactFlash controller waveforms for attribute memory read access FSMC_NCE4_1 tv(NCE4_1-A) FSMC_NCE4_2 th(NCE4_1-AI) High FSMC_A[10:0] FSMC_NIOWR FSMC_NIORD td(NREG-NCE4_1) th(NCE4_1-NREG) FSMC_NREG FSMC_NWE td(NCE4_1-NOE) tw(NOE) td(NOE-NCE4_1) FSMC_NOE tsu(D-NOE) th(NOE-D) FSMC_D[15:0](1) ai14897b 1. Only data bits 0...7 are read (bits 8...15 are disregarded).
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STM32F405xx, STM32F407xx Electrical characteristics Figure 63. PC Card/CompactFlash controller waveforms for attribute memory write access FSMC_NCE4_1 FSMC_NCE4_2 High tv(NCE4_1-A) th(NCE4_1-AI) FSMC_A[10:0] FSMC_NIOWR FSMC_NIORD td(NREG-NCE4_1) th(NCE4_1-NREG) FSMC_NREG td(NCE4_1-NWE) tw(NWE) FSMC_NWE td(NWE-NCE4_1) FSMC_NOE tv(NWE-D) FSMC_D[7:0](1) ai14898b 1. Only data bits 0...7 are driven (bits 8...15 remains Hi-Z). Figure 64.
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Electrical characteristics STM32F405xx, STM32F407xx Figure 65. PC Card/CompactFlash controller waveforms for I/O space write access &3-#?.#% ? &3-#?.#% ? TV .#%X ! TH .#% ? !) &3-#?!; = &3-#?.2%' &3-#?.7% &3-#?./% &3-#?.)/2$ TD .#% ? .)/72 TW .)/72 &3-#?.)/72 !44X(): TV .)/72 $ TH .)/72 $ &3-#?$; = AI C Table 79.
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STM32F405xx, STM32F407xx Table 80. Electrical characteristics Switching characteristics for PC Card/CF read and write cycles in I/O space(1)(2) Symbol Parameter tw(NIOWR) FSMC_NIOWR low width tv(NIOWR-D) FSMC_NIOWR low to FSMC_D[15:0] valid th(NIOWR-D) FSMC_NIOWR high to FSMC_D[15:0] invalid Min Max Unit 8THCLK –1 - ns - 5THCLK– 1 ns 8THCLK– 2 - ns - 5THCLK+ 2.5 ns 5THCLK–1.
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Electrical characteristics STM32F405xx, STM32F407xx Figure 66. NAND controller waveforms for read access &3-#?.#%X !,% &3-#?! #,% &3-#?! &3-#?.7% TD !,% ./% TH ./% !,% &3-#?./% .2% TSU $ ./% TH ./% $ &3-#?$; = AI C Figure 67. NAND controller waveforms for write access &3-#?.#%X !,% &3-#?! #,% &3-#?! TD !,% .7% TH .7% !,% &3-#?.7% &3-#?./% .2% TV .7% $ TH .
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STM32F405xx, STM32F407xx Electrical characteristics Figure 68. NAND controller waveforms for common memory read access &3-#?.#%X !,% &3-#?! #,% &3-#?! TD !,% ./% TH ./% !,% &3-#?.7% TW ./% &3-#?./% TSU $ ./% TH ./% $ &3-#?$; = AI C Figure 69. NAND controller waveforms for common memory write access &3-#?.#%X !,% &3-#?! #,% &3-#?! TD !,% ./% TW .7% TH ./% !,% &3-#?.7% &3-#?./% TD $ .7% TV .7% $ TH .7% $ &3-#?$; = AI C Table 81.
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Electrical characteristics STM32F405xx, STM32F407xx Switching characteristics for NAND Flash write cycles(1) Table 82.
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STM32F405xx, STM32F407xx Electrical characteristics Figure 71. SD default mode CK tOVD tOHD D, CMD (output) ai14888 Table 84.
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Package characteristics STM32F405xx, STM32F407xx 6 Package characteristics 6.1 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
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STM32F405xx, STM32F407xx Package characteristics Figure 73. Recommended footprint(1)(2) Figure 72. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline(1) A 48 33 A2 0.3 A1 E 49 b E1 12.7 32 0.5 10.3 e 10.3 64 17 1.2 1 D1 c 7.8 L1 D 16 12.7 L ai14398b ai14909 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 86. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ A Max Min Typ 1.
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Package characteristics STM32F405xx, STM32F407xx Figure 74. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline(1) Figure 75. Recommended footprint(1)(2) 0.25 mm 0.10 inch GAGE PLANE k D L D1 75 51 L1 D3 51 75 76 C 76 50 0.5 50 0.3 16.7 b 14.3 E3 E1 E 100 100 26 1.2 26 Pin 1 1 identification 25 1 C ccc 25 12.3 e A1 16.7 A2 ai14906 A SEATING PLANE C 1L_ME 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 87.
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STM32F405xx, STM32F407xx Package characteristics Figure 76. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline(1) Figure 77. Recommended footprint(1)(2) Seating plane C A A2 A1 c b ccc 0.25 mm gage plane C D k 108 109 73 1.35 72 0.35 D1 A1 D3 108 L 73 0.5 L1 72 109 17.85 19.9 E1 E 144 22.6 37 E3 1 36 19.9 22.6 a 144 Pin 1 identification 37 36 1 e ME_1A 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 88.
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Package characteristics STM32F405xx, STM32F407xx Figure 78. UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm, package outline C Seating plane A2 ddd A4 C A A3 A1 A D B Ball A1 e F A F E e R 15 Øb 1 (176 balls) Ø eee M C A Ø fff M B A0E7_ME C 1. Drawing is not to scale. Table 89. UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.460 0.530 0.600 0.0181 0.0209 0.
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STM32F405xx, STM32F407xx Package characteristics Figure 79. LQFP176 24 x 24 mm, 144-pin low-profile quad flat package outline C Seating plane 0.25 mm gauge plane A A2 k c A1 ccc C A1 HD L D L1 ZD ZE 89 132 88 133 b E 176 Pin 1 identification HE 45 44 1 e 1T_ME 1. Drawing is not to scale. Table 90. LQFP176, 24 x 24 mm, 144-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ A Max Min Typ 1.600 Max 0.0630 A1 0.050 0.150 0.0020 A2 1.
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Package characteristics 6.2 STM32F405xx, STM32F407xx Thermal characteristics The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max x ΘJA) Where: ● TA max is the maximum ambient temperature in °C, ● ΘJA is the package junction-to-ambient thermal resistance, in °C/W, ● PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), ● PINT max is the product of IDD and VDD, expressed in Watts.
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STM32F405xx, STM32F407xx Part numbering 7 Part numbering Table 92.
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Application block diagrams Appendix A A.1 STM32F405xx, STM32F407xx Application block diagrams Main applications versus package Table 93 gives examples of configurations for each package. Table 93.
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STM32F405xx, STM32F407xx A.2 Application block diagrams Application example with regulator OFF Figure 80. Regulator OFF/internal reset ON 0OWER DOWN RESET RISEN AFTER 6#!0? 6#!0? STABILIZATION 0OWER DOWN RESET RISEN BEFORE 6#!0? 6#!0? STABILIZATION 6#!0? MONITORING %XT RESET CONTROLLER ACTIVE WHEN 6 #!0? 6 !PPLICATION RESET SIGNAL OPTIONAL 6$$ 0! 6$$ 6$$ .234 !PPLICATION RESET SIGNAL OPTIONAL 0! 6$$ .234 0$2?/. 0$2?/.
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Application block diagrams A.3 STM32F405xx, STM32F407xx USB OTG full speed (FS) interface solutions Figure 82. USB controller configured as peripheral-only and used in Full speed mode 6$$ 6 TO 6$$ 6OLATGE REGULATOR 6"53 0! 0" $- /3#?). 0! 0" $0 0! 0" 633 /3#?/54 53" 3TD " CONNECTOR 34- & XX -3 6 1. External voltage regulator only needed when building a VBUS powered device. 2.
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STM32F405xx, STM32F407xx Application block diagrams Figure 84. USB controller configured in dual mode and used in full speed mode 6$$ 6 TO 6$$ VOLTAGE REGULATOR 6$$ '0)/ )21 /VERCURRENT #URRENT LIMITER POWER SWITCH 6 0WR 34- & XX 0! 0" 0! 0" /3#?). /3#?/54 0! 0" 0! 0" 6"53 $$0 )$ 633 53"MICRO !" CONNECTOR '0)/ %. -3 6 1. External voltage regulator only needed when building a VBUS powered device. 2.
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Application block diagrams A.4 STM32F405xx, STM32F407xx USB OTG high speed (HS) interface solutions Figure 85. USB controller configured as peripheral, host, or dual-mode and used in high speed mode 34- & XX &3 0(9 53" (3 /4' #TRL $0 $- NOT CONNECTED $0 5,0)?#,+ $- 5,0)?$; = 5,0) )$ 5,0)?$)2 6"53 5,0)?340 53" CONNECTOR 633 5,0)?.84 (IGH SPEED /4' 0(9 0,, 84 OR -(Z 84 -#/ OR -#/ 8) -3 6 1. It is possible to use MCO1 or MCO2 to save a crystal.
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STM32F405xx, STM32F407xx A.5 Application block diagrams Complete audio player solutions Two solutions are offered, illustrated in Figure 86 and Figure 87. Figure 86 shows storage media to audio DAC/amplifier streaming using a software Codec. This solution implements an audio crystal to provide audio class I2S accuracy on the master clock (0.5% error maximum, see the Serial peripheral interface section in the reference manual for details). Figure 86.
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Application block diagrams STM32F405xx, STM32F407xx Figure 88. Audio player solution using PLL, PLLI2S, USB and 1 crystal 34- & XX $IV BY - /3# 84!, -(Z OR -(Z 0,, X . $IV BY 0 #ORTEX - & CORE UP TO -(Z $IV BY 1 /4' -(Z 0,,) 3 X . $IV BY 2 0(9 -#/ 02% -#/ 02% -#/ -#/ ) 3 ACCURACY -#,+ IN -#,+ OUT 3#,+ $!# !UDIO AMPLI -3 6 Figure 89. Audio PLL (PLLI2S) providing accurate I2S clock PLLI2S Phase lock detector CLKIN /M M=1,2,3,..
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STM32F405xx, STM32F407xx Application block diagrams Figure 90. Master clock (MCK) used to drive the external audio DAC I2S controller I2S_CK I2S_MCK = 256 × FSAUDIO = 11.2896 MHz for FSAUDIO = 44.1 kHz = 12.2880 MHz for FSAUDIO = 48.0 kHz /I2SD 2,3,4,..,129 I2S_SCK(1) = I2S_MCK/8 for 16-bit stereo = I2S_MCK/4 for 32-bit stereo /8 /(2 x 16) FSAUDIO for 16-bit stereo /4 /(2 x 32) FSAUDIO for 32-bit stereo ai16042 1.
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Application block diagrams A.6 STM32F405xx, STM32F407xx Ethernet interface solutions Figure 92. MII mode using a 25 MHz crystal 34- -#5 -))?48?#,+ -))?48?%. -))?48$; = -))?#23 -))?#/, %THERNET -!# (#,+ )%%% 040 4IMER INPUT TRIGGER 4IMESTAMP 4)- COMPARATOR %THERNET 0(9 -)) PINS -))?28?#,+ -))?28$; = -))?28?$6 -))?28?%2 -)) -$# PINS -$)/ -$# 003?/54 84!, -(Z /3# (#,+ 0,, -#/ -#/ 0(9?#,+ -(Z 84 -3 6 1. fHCLK must be greater than 25 MHz. 2.
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STM32F405xx, STM32F407xx Application block diagrams Figure 94. RMII with a 25 MHz crystal and PHY with PLL 34- & -#5 %THERNET 0(9 2-))?48?%. %THERNET -!# 2-))?48$; = 2-))?28$; = (#,+ )%%% 040 2-))?#28?$6 2-))?2%&?#,+ 2-)) PINS 2%&?#,+ -$)/ 4IMER INPUT TRIGGER 4IMESTAMP 4)- COMPARATOR 2-)) -$# PINS -$# OR OR -(Z SYNCHRONOUS -(Z 84!, -(Z /3# 0,, (#,+ 0,, -#/ -#/ 0(9?#,+ -(Z 84 -3 6 1. fHCLK must be greater than 25 MHz. 2.
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Revision history 8 STM32F405xx, STM32F407xx Revision history Table 94. Document revision history Date Revision 15-Sep-2011 1 Initial release. 2 Added WLCSP90 package on cover page. Renamed USART4 and USART5 into UART4 and UART5, respectively. Updated number of USB OTG HS and FS in Table 2: STM32F405xx and STM32F407xx: features and peripheral counts.
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STM32F405xx, STM32F407xx Table 94. Revision history Document revision history (continued) Date 24-Jan-2012 Revision Changes Added V12 in Table 16: Embedded reset and power control block characteristics. Updated Table 17: Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator disabled) and Table 18: Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled) or RAM.
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Revision history STM32F405xx, STM32F407xx Table 94. Document revision history (continued) Date 24-Jan-2012 166/167 Revision Changes Updated Table 57: USB FS clock timing parameters and Table 59: USB HS clock timing parameters Updated Table 65: ADC characteristics. Updated Table 66: ADC accuracy at fADC = 30 MHz. Updated Note 1 in Table 70: DAC characteristics. Section 5.3.
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STM32F405xx, STM32F407xx Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.