Datasheet

DocID022152 Rev 8 149/202
STM32F405xx, STM32F407xx Electrical characteristics
Figure 59. Synchronous multiplexed PSRAM write timings
Table 80. Synchronous multiplexed PSRAM write timings
(1)(2)
Symbol Parameter Min Max Unit
t
w(CLK)
FSMC_CLK period 2T
HCLK
-ns
t
d(CLKL-NExL)
FSMC_CLK low to FSMC_NEx low (x=0..2) - 1 ns
t
d(CLKL-NExH)
FSMC_CLK low to FSMC_NEx high (x= 0…2) 1 - ns
t
d(CLKL-NADVL)
FSMC_CLK low to FSMC_NADV low - 0 ns
t
d(CLKL-
NADVH)
FSMC_CLK low to FSMC_NADV high 0 - ns
t
d(CLKL-AV)
FSMC_CLK low to FSMC_Ax valid (x=16…25) - 0 ns
t
d(CLKL-AIV)
FSMC_CLK low to FSMC_Ax invalid (x=16…25) 8 - ns
t
d(CLKL-NWEL)
FSMC_CLK low to FSMC_NWE low - 0.5 ns
t
d(CLKL-NWEH)
FSMC_CLK low to FSMC_NWE high 0 - ns
t
d(CLKL-ADIV)
FSMC_CLK low to FSMC_AD[15:0] invalid 0 - ns
t
d(CLKL-DATA)
FSMC_A/D[15:0] valid data after FSMC_CLK
low
-3ns
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