Datasheet

Electrical characteristics STM32F405xx, STM32F407xx
134/202 DocID022152 Rev 8
t
lat
(4)
Injection trigger conversion
latency
f
ADC
= 30 MHz - - 0.100 µs
--3
(7)
1/f
ADC
t
latr
(4)
Regular trigger conversion
latency
f
ADC
= 30 MHz - - 0.067 µs
--2
(7)
1/f
ADC
t
S
(4)
Sampling time
f
ADC
= 30 MHz 0.100 - 16 µs
- 3 - 480 1/f
ADC
t
STAB
(4)
Power-up time - - 2 3 µs
t
CONV
(4)
Total conversion time (including
sampling time)
f
ADC
= 30 MHz
12-bit resolution
0.50 - 16.40 µs
f
ADC
= 30 MHz
10-bit resolution
0.43 - 16.34 µs
f
ADC
= 30 MHz
8-bit resolution
0.37 - 16.27 µs
f
ADC
= 30 MHz
6-bit resolution
0.30 - 16.20 µs
9 to 492 (t
S
for sampling +n-bit resolution for successive
approximation)
1/f
ADC
f
S
(4)
Sampling rate
(f
ADC
= 30 MHz, and
t
S
= 3 ADC cycles)
12-bit resolution
Single ADC
- - 2 Msps
12-bit resolution
Interleave Dual ADC
mode
- - 3.75 Msps
12-bit resolution
Interleave Triple ADC
mode
- - 6 Msps
I
VREF+
(4)
ADC V
REF
DC current
consumption in conversion
mode
- - 300 500 µA
I
VDDA
(4)
ADC V
DDA
DC current
consumption in conversion
mode
--1.61.8mA
1. V
DD
/V
DDA
minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of
an external power supply supervisor (refer to Section : Internal reset OFF).
2. It is recommended to maintain the voltage difference between V
REF+
and V
DDA
below 1.8 V.
3. V
DDA
-V
REF+
< 1.2 V.
4. Guaranteed by characterization.
5. V
REF+
is internally connected to V
DDA
and V
REF-
is internally connected to V
SSA
.
6. R
ADC
maximum value is given for V
DD
=1.8 V, and minimum value for V
DD
=3.3 V.
7. For external triggers, a delay of 1/f
PCLK2
must be added to the latency specified in Table 67.
Table 67. ADC characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit
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