Datasheet

Electrical characteristics STM32F401xD STM32F401xE
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6.3.19 Communications interfaces
I
2
C interface characteristics
The I2C interface meets the requirements of the standard I
2
C communication protocol with
the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” open-
drain. When configured as open-drain, the PMOS connected between the I/O pin and V
DD is
disabled, but is still present.
The I
2
C characteristics are described in Table59. Refer also to Section 6.3.16: I/O port
characteristics for more details on the input/output alternate function characteristics (SDA
and SCL).
The I
2
C bus interface supports standard mode (up to 100 kHz) and fast mode (up to 400
kHz). The I
2C bus frequency can be increased up to 1 MHz. For more details about the
complete solution, please contact your local ST sales representative.
Table 59. I
2
C characteristics
Symbol Parameter
Standard mode I
2
C
(1)
1.
Guaranteed by design, not tested in production.
Fast mode I
2
C
(1)(2)
2. f
PCLK1
must be at least 2 MHz to achieve standard mode I
2
C frequencies. It must be at least 4 MHz to
achieve fast mode I
2
C frequencies, and a multiple of 10 MHz to reach the 400 kHz maximum I
2
C fast mode
clock.
Unit
Min Max Min Max
t
w(SCLL)
SCL clock low time 4.7 - 1.3 -
µs
t
w(SCLH)
SCL clock high time 4.0 - 0.6 -
t
su(SDA)
SDA setup time 250 - 100 -
ns
t
h(SDA)
SDA data hold time 0 - 0 900
(3)
3. The maximum data hold time has only to be met if the interface does not stretch the low period of SCL
signal.
t
r(SDA)
t
r(SCL)
SDA and SCL rise time - 1000 300
t
f(SDA)
t
f(SCL)
SDA and SCL fall time - 300 - 300
t
h(STA)
Start condition hold time 4.0 - 0.6 -
µs
t
su(STA)
Repeated Start condition
setup time
4.7 - 0.6 -
t
su(STO)
Stop condition setup time 4.0 - 0.6 - µs
t
w(STO:STA)
Stop to Start condition time
(bus free)
4.7 - 1.3 - µs
C
b
Capacitive load for each bus
line
- 400 - 400 pF
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