Datasheet

DocID025644 Rev 3 83/135
STM32F401xD STM32F401xE Electrical characteristics
114
I
DD(PLL)
(4)
PLL power consumption on VDD
VCO freq = 192 MHz
VCO freq = 432 MHz
0.15
0.45
-
0.40
0.75
mA
I
DDA(PLL)
(4)
PLL power consumption on
VDDA
VCO freq = 192 MHz
VCO freq = 432 MHz
0.30
0.55
-
0.40
0.85
1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared
between PLL and PLLI2S.
2. Guaranteed by design, not tested in production.
3. The use of 2 PLLs in parallel could degraded the Jitter up to +30%.
4. Guaranteed by characterization, not tested in production.
Table 41. Main PLL characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit
Table 42. PLLI2S (audio PLL) characteristics
Symbol Parameter Conditions Min Typ Max Unit
f
PLLI2S_IN
PLLI2S input clock
(1)
0.95
(2)
12.10
MHzf
PLLI2S_OUT
PLLI2S multiplier output clock - - 216
f
VCO_OUT
PLLI2S VCO output 192 - 432
t
LOCK
PLLI2S lock time
VCO freq = 192 MHz 75 - 200
µs
VCO freq = 432 MHz 100 - 300
Jitter
(3)
Master I2S clock jitter
Cycle to cycle at
12.288 MHz on
48 KHz period,
N=432, R=5
RMS - 90 -
peak
to
peak
- ±280 -
ps
Average frequency of
12.288 MHz
N = 432, R = 5
on 1000 samples
-90 -
WS I2S clock jitter
Cycle to cycle at 48 KHz
on 1000 samples
- 400 -
I
DD(PLLI2S)
(4)
PLLI2S power consumption on
V
DD
VCO freq = 192 MHz
VCO freq = 432 MHz
0.15
0.45
-
0.40
0.75
mA
I
DDA(PLLI2S)
(4)
PLLI2S power consumption on
V
DDA
VCO freq = 192 MHz
VCO freq = 432 MHz
0.30
0.55
-
0.40
0.85
1. Take care of using the appropriate division factor M to have the specified PLL input clock values.
2. Guaranteed by design, not tested in production.
3. Value given with main PLL running.
4. Guaranteed by characterization, not tested in production.
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