Datasheet

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STM32F401xD STM32F401xE Electrical characteristics
114
6.3.3 Operating conditions at power-up/power-down (regulator ON)
Subject to general operating conditions for T
A
.
Table 17. Operating conditions at power-up / power-down (regulator ON)
6.3.4 Operating conditions at power-up / power-down (regulator OFF)
Subject to general operating conditions for T
A
.
Note: This feature is only available for UFBGA100 package.
Symbol Parameter Min Max Unit
t
VDD
V
DD
rise time rate 20 ∞
µs/V
V
DD
fall time rate 20 ∞
Table 18. Operating conditions at power-up / power-down (regulator OFF)
(1)
1. To reset the internal logic at power-down, a reset must be applied on pin PA0 when V
DD
reach below
1.08 V.
Symbol Parameter Conditions Min Max Unit
t
VDD
V
DD
rise time rate Power-up 20 ∞
µs/V
V
DD
fall time rate Power-down 20 ∞
t
VCAP
V
CAP_1
and V
CAP_2
rise time rate Power-up 20 ∞
V
CAP_1
and V
CAP_2
fall time rate Power-down 20 ∞
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