Datasheet

DocID025644 Rev 3 21/135
STM32F401xD STM32F401xE Functional overview
54
The V
DD
specified threshold, below which the device must be maintained under reset, is
1.7 V (see Figure 6).
A comprehensive set of power-saving mode allows to design low-power applications.
When the internal reset is OFF, the following integrated features are no longer supported:
• The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled.
• The brownout reset (BOR) circuitry must be disabled.
• The embedded programmable voltage detector (PVD) is disabled.
• V
BAT
functionality is no more available and VBAT pin should be connected to V
DD
.
3.15 Voltage regulator
The regulator has four operating modes:
• Regulator ON
– Main regulator mode (MR)
– Low power regulator (LPR)
– Power-down
• Regulator OFF
3.15.1 Regulator ON
On packages embedding the BYPASS_REG pin, the regulator is enabled by holding
BYPASS_REG low. On all other packages, the regulator is always enabled.
Figure 6. PDR_ON control with internal reset OFF
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