Datasheet

DocID025644 Rev 3 101/135
STM32F401xD STM32F401xE Electrical characteristics
114
Figure 34. SPI timing diagram - slave mode and CPHA = 0
Figure 35. SPI timing diagram - slave mode and CPHA = 1
(1)
t
v(MO)
Data output valid time Master mode (after enable edge) - 3 5 ns
t
h(MO)
Data output hold time
Master mode (after enable edge) 2 - - ns
1. Guaranteed by characterization, not tested in production.
2. Maximum frequency in Slave transmitter mode is determined by the sum of t
v(SO)
and t
su(MI)
which has to fit into SCK low or
high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master
having t
su(MI)
= 0 while Duty(SCK) = 50%
Table 61. SPI dynamic characteristics
(1)
(continued)
Symbol Parameter Conditions Min Typ Max Unit
ai14134c
SCK Input
CPHA= 0
MOSI
INPUT
MISO
OUT PUT
CPHA= 0
MS B O U T
MSB IN
BI T6 OU T
LSB IN
LSB OUT
CPOL=0
CPOL=1
BIT1 IN
NSS input
t
SU(NSS)
t
c(SCK)
t
h(NSS)
t
a(SO)
t
w(SCKH)
t
w(SCKL)
t
v(SO)
t
h(SO)
t
r(SCK)
t
f(SCK)
t
dis(SO)
t
su(SI)
t
h(SI)
ai14135
SCK Input
CPHA=1
MOSI
INPUT
MISO
OUT PUT
CPHA=1
MS B O U T
MSB IN
BI T6 OU T
LSB IN
LSB OUT
CPOL=0
CPOL=1
BIT1 IN
t
SU(NSS)
t
c(SCK)
t
h(NSS)
t
a(SO)
t
w(SCKH)
t
w(SCKL)
t
v(SO)
t
h(SO)
t
r(SCK)
t
f(SCK)
t
dis(SO)
t
su(SI)
t
h(SI)
NSS input
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