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This is information on a product in full production.

January 2015 DocID025644 Rev 3 1/135

STM32F401xD STM32F401xE

ARM

Cortex

-M4 32b MCU+FPU, 105 DMIPS,

512KB Flash/96KB RAM, 11 TIMs, 1 ADC, 11 comm. interfaces

Datasheet - production data

Features

• Core: ARM

32-bit Cortex

-M4 CPU with

FPU, Adaptive real-time accelerator (ART

Accelerator™) allowing 0-wait state execution

from Flash memory, frequency up to 84 MHz,

memory protection unit,

105 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1),

and DSP instructions

• Memories

– up to 512 Kbytes of Flash memory

– up to 96 Kbytes of SRAM

• Clock, reset and supply management

– 1.7 V to 3.6 V application supply and I/Os

– POR, PDR, PVD and BOR

– 4-to-26 MHz crystal oscillator

– Internal 16 MHz factory-trimmed RC

– 32 kHz oscillator for RTC with calibration

– Internal 32 kHz RC with calibration

• Power consumption

– Run: 146 µA/MHz (peripheral off)

– Stop (Flash in Stop mode, fast wakeup

time): 42 µA Typ @ 25C; 65 µA max

@25 °C

– Stop (Flash in Deep power down mode,

fast wakeup time): down to 10 µA @ 25 °C;

30 µA max @25 °C

– Standby: 2.4 µA @25 °C / 1.7 V without

RTC; 12 µA @85 °C @1.7 V

–V

BAT

supply for RTC: 1 µA @25 °C

• 1×12-bit, 2.4 MSPS A/D converter: up to 16

channels

• General-purpose DMA: 16-stream DMA

controllers with FIFOs and burst support

• Up to 11 timers: up to six 16-bit, two 32-bit

timers up to 84 MHz, each with up to four

IC/OC/PWM or pulse counter and quadrature

(incremental) encoder input, two watchdog

timers (independent and window) and a

SysTick timer

• Debug mode

– Serial wire debug (SWD) & JTAG

interfaces

–Cortex

-M4 Embedded Trace Macrocell™

• Up to 81 I/O ports with interrupt capability

– Up to 78 fast I/Os up to 42 MHz

– All I/O ports are 5 V-tolerant

• Up to 12 communication interfaces

– Up to 3 x I

C interfaces (SMBus/PMBus)

– Up to 3 USARTs (2 x 10.5 Mbit/s,

1 x 5.25 Mbit/s), ISO 7816 interface, LIN,

IrDA, modem control)

– Up to 4 SPIs (up to 42Mbit/s at

CPU

= 84 MHz), SPI2 and SPI3 with muxed

full-duplex I

S to achieve audio class

accuracy via internal audio PLL or external

clock

– SDIO interface

– Advanced connectivity: USB 2.0 full-speed

device/host/OTG controller with on-chip

PHY

• CRC calculation unit

• 96-bit unique ID

• RTC: subsecond accuracy, hardware calendar

• All packages (WLCSP49, LQFP64/100,

UFQFPN48, UFBGA100) are ECOPACK

Table 1. Device summary

Reference Part number

STM32F401xD

STM32F401CD,

STM32F401RD, STM32F401VD

STM32F401xE

STM32F401CE,

STM32F401RE, STM32F401VE

LQFP100 (14 × 14 mm)

LQFP64 (10 × 10 mm)

UFQFPN48

(7 × 7 mm)

UFBGA100

(7 × 7 mm)

WLCSP49

(3.06 x 3.06 mm)

)%*$

www.st.com

Downloaded from Arrow.com.

Summary of content (135 pages)

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STM32F401xD STM32F401xE ARM® Cortex®-M4 32b MCU+FPU, 105 DMIPS, 512KB Flash/96KB RAM, 11 TIMs, 1 ADC, 11 comm. interfaces Datasheet - production data Features ® ® • Core: ARM 32-bit Cortex -M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 84 MHz, memory protection unit, 105 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.
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Contents STM32F401xD STM32F401xE Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1 ARM® Cortex®-M4 with FPU core with embedded Flash and SRAM . . . 15 3.
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STM32F401xD STM32F401xE Contents 3.19.3 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.19.4 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.19.5 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.20 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.
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Contents 7 STM32F401xD STM32F401xE 6.3.6 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.3.7 Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.3.8 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.3.9 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.3.10 PLL characteristics . . . . . . . . . . . . . . . . . . .
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STM32F401xD STM32F401xE List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Device summary . . . . . . . . . . . . . . .
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List of tables Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. 6/135 Downloaded from Arrow.com.
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STM32F401xD STM32F401xE List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42.
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List of figures Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. 8/135 Downloaded from Arrow.com. STM32F401xD STM32F401xE WLCSP49 0.4 mm pitch wafer level chip size recommended footprint . . . . . . . . . . . . . . 117 Example of WLCSP49 marking (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 UFQFPN48, 7 x 7 mm, 0.5 mm pitch, package outline. . . . . . . . . . . .
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STM32F401xD STM32F401xE 1 Introduction Introduction This datasheet provides the description of the STM32F401xD/xE line of microcontrollers. The STM32F401xD/xE datasheet should be read in conjunction with RM0368 reference manual which is available from the STMicroelectronics website www.st.com. It includes all information concerning Flash memory programming. For information on the Cortex-M4 core, please refer to the Cortex-M4 programming manual (PM0214) available from www.st.com.
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Description 2 STM32F401xD STM32F401xE Description The STM32F401XD/XE devices are based on the high-performance ARM® Cortex® -M4 32bit RISC core operating at a frequency of up to 84 MHz. Its Cortex®-M4 core features a Floating point unit (FPU) single precision which supports all ARM single-precision dataprocessing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security.
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STM32F401xD STM32F401xE Description Table 2.
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Description 2.1 STM32F401xD STM32F401xE Compatibility with STM32F4 series The STM32F401xD/xE are fully software and feature compatible with the STM32F4 series (STM32F42x, STM32F43x, STM32F41x, STM32F405 and STM32F407) The STM32F401xD/xE can be used as drop-in replacement of the other STM32F4 products but some slight changes have to be done on the PCB board. Figure 1. Compatible board design for LQFP100 package 670 ) [ 3% QRW DYDLODEOH DQ\PRUH 5HSODFHG E\ 9 &$3
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STM32F401xD STM32F401xE Description Figure 2. Compatible board design for LQFP64 package 670 ) [ 3% 9&$3 9'' 3% 3% 9'' 9&$3 3$ 3$ 3$ 3$ 3$ 3$ 3& 3& 3& 3& 3% 3% 3% 3% 9'' 966 3% QRW DYDLODEOH DQ\PRUH 5HSODFHG E\ 9&$3 9'' 966 3$ 3$ 3$ 3$ 3$ 3$ 3& 3& 3& 3& 3% 3% 3% 3% 9'' 966 3% 3% 9&$3 966 9''
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Description STM32F401xD STM32F401xE Figure 3. STM32F401xD/xE block diagram -7$* 6: 038 19,& (70 ' %86 '0$ 6WUHDPV ),)2 '0$ 6WUHDPV ),)2 .% )ODVK .% 65$0 $+% 0+] &)&/ 6 %86 $&&(/ &$&+( )38 0(9 $50 &RUWH[ 0 0+] , %86 $+% EXV PDWUL[ 6 0 1-7567 -7', -7&. 6:&/. -7'2 6:' -7'2 75$&(&/.
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STM32F401xD STM32F401xE Functional overview 3 Functional overview 3.1 ARM® Cortex®-M4 with FPU core with embedded Flash and SRAM The ARM® Cortex®-M4 with FPU processor is the latest generation of ARM processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts.
PAGE 16
Functional overview 3.4 STM32F401xD STM32F401xE Embedded Flash memory The devices embed 512 Kbytes of Flash memory available for storing programs and data. 3.5 CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity.
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STM32F401xD STM32F401xE Functional overview Figure 4. Multi-AHB matrix 6 6 6 6 '0$B3 *3 '0$ '0$B0(0 '0$B0(0 '0$B3, 6 EXV *3 '0$ 6 0 ,&2'( 0 '&2'( $&&(/ 6 ' EXV , EXV $50 &RUWH[ 0 )ODVK N% 0 65$0 .E\WHV 0 $+% SHULSK $3% 0 $+% SHULSK $3% %XV PDWUL[ 6 06 9 3.8 DMA controller (DMA) The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each.
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Functional overview 3.9 STM32F401xD STM32F401xE Nested vectored interrupt controller (NVIC) The devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 62 maskable interrupt channels plus the 16 interrupt lines of the Cortex®-M4 with FPU.
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STM32F401xD STM32F401xE 3.12 Functional overview Boot modes At startup, boot pins are used to select one out of three boot options: • Boot from user Flash • Boot from system memory • Boot from embedded SRAM The boot loader is located in system memory.
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Functional overview STM32F401xD STM32F401xE 3.14 Power supply supervisor 3.14.1 Internal reset ON This feature is available for VDD operating voltage range 1.8 V to 3.6 V. The internal power supply supervisor is enabled by holding PDR_ON high. The device has an integrated power-on reset (POR) / power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry. At power-on, POR is always active, and ensures proper operation starting from 1.8 V. After the 1.
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STM32F401xD STM32F401xE Functional overview The VDD specified threshold, below which the device must be maintained under reset, is 1.7 V (see Figure 6). A comprehensive set of power-saving mode allows to design low-power applications. When the internal reset is OFF, the following integrated features are no longer supported: • The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled. • The brownout reset (BOR) circuitry must be disabled.
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Functional overview STM32F401xD STM32F401xE There are three power modes configured by software when the regulator is ON: • MR is used in the nominal regulation mode (With different voltage scaling in Run) In Main regulator mode (MR mode), different voltage scaling are provided to reach the best compromise between maximum frequency and dynamic power consumption. • LPR is used in the Stop modes The LP regulator mode is configured by software when entering Stop mode.
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STM32F401xD STM32F401xE Functional overview Figure 7. Regulator OFF 9 ([WHUQDO 9&$3B SRZHU $SSOLFDWLRQ UHVHW VXSSO\ VXSHUYLVRU ([W UHVHW FRQWUROOHU DFWLYH VLJQDO RSWLRQDO ZKHQ 9&$3B 0LQ 9 9'' 3$ 9'' 1567 %<3$66B5(* 9 9&$3B 9&$3B DL 9 The following conditions must be respected: Note: • VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection between power domains.
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Functional overview STM32F401xD STM32F401xE Figure 8. Startup in regulator OFF: slow VDD slope power-down reset risen after VCAP_1/VCAP_2 stabilization 9'' 3'5 9 9 0LQ 9 9&$3B 9&$3B WLPH 1567 WLPH 06Y 9 1. This figure is valid whatever the internal reset mode (ON or OFF). Figure 9. Startup in regulator OFF mode: fast VDD slope power-down reset risen before VCAP_1/VCAP_2 stabilization 9'' 3'5 9 9&$3B 9&$3B 9 0LQ 9 1567 WLPH 3$ DVVHUWHG H[WHUQDOO\ WLPH 1.
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STM32F401xD STM32F401xE 3.15.3 Functional overview Regulator ON/OFF and internal power supply supervisor availability Table 3.
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Functional overview STM32F401xD STM32F401xE The RTC and backup registers are supplied through a switch that is powered either from the VDD supply when present or from the VBAT pin. 3.17 Low-power modes The devices support three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: • Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.
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STM32F401xD STM32F401xE 3.19 Functional overview Timers and watchdogs The devices embed one advanced-control timer, seven general-purpose timers and two watchdog timers. All timer counters can be frozen in debug mode. Table 4 compares the features of the advanced-control and general-purpose timers. Table 4.
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Functional overview STM32F401xD STM32F401xE If configured as standard 16-bit timers, it has the same features as the general-purpose TIMx timers. If configured as a 16-bit PWM generator, it has full modulation capability (0100%). The advanced-control timer can work together with the TIMx timers via the Timer Link feature for synchronization or event chaining. TIM1 supports independent DMA request generation. 3.19.
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STM32F401xD STM32F401xE 3.19.5 Functional overview SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard downcounter. It features: 3.20 • A 24-bit downcounter • Autoreload capability • Maskable system interrupt generation when the counter reaches 0 • Programmable clock source. Inter-integrated circuit interface (I2C) Up to three I2C bus interfaces can operate in multimaster and slave modes.
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Functional overview STM32F401xD STM32F401xE Table 6. USART feature comparison Max. baud Max. baud USART Standard Modem SPI Smartcard rate in Mbit/s rate in Mbit/s APB LIN irDA name features (RTS/CTS) master (ISO 7816) (oversampling (oversampling mapping by 16) by 8) USART1 X X X X X X 5.25 10.5 APB2 (max. 84 MHz) USART2 X X X X X X 2.62 5.25 APB1 (max. 42 MHz) USART6 X N.A X X X X 5.25 10.5 APB2 (max. 84 MHz) 3.
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STM32F401xD STM32F401xE 3.25 Functional overview Secure digital input/output interface (SDIO) An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit. The interface allows data transfer at up to 48 MHz, and is compliant with the SD Memory Card Specification Version 2.0. The SDIO Card Specification Version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit.
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Functional overview STM32F401xD STM32F401xE The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1, TIM2, TIM3, TIM4 or TIM5 timer. 3.
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STM32F401xD STM32F401xE 4 Pinouts and pin description Pinouts and pin description Figure 10. STM32F401xD/xE WLCSP49 pinout $ 9'' 966 %227 3% 3% 3$ 3$ % 9%$7 3'5 B21 3% 3% 3$ 9'' 966 3% 3% 3$ 3$ 3$ 3% 966 3$ 3$ & 3& 3& 26& B,1 26& B287 ' 3+ 3+ 3& 26&B,1 26&B287 ( 1567 966$ 95() 3$ 3$ 3% 3% 3% ) 9''$ 95() 3$ 3$ 3$ 3$ 9'' 3% * 3$ 3$ 3% 3% 3% 9&$3 3% 06 9 1.
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Pinouts and pin description STM32F401xD STM32F401xE 0! 0! 0! 0# /3# ?/54 0! 0( /3#?). 0! 0( /3#?/54 0! .234 0! 633! 62%& 0! 6$$! 62%& 0" 0! 0" 0! 0" 0! 0" 0! 0! 0! 0! 0" 0" 0" 0" 6#!0 633 6$$ Downloaded from Arrow.com. 5&1&0. 1. The above figure shows the package top view.
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STM32F401xD STM32F401xE Pinouts and pin description 0# 0# /3# ?). 0# /3# ?/54 0( /3#?). 0! 633 6$$ 0( /3#?/54 .
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Pinouts and pin description STM32F401xD STM32F401xE 6$$ 633 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! Figure 13.
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STM32F401xD STM32F401xE Pinouts and pin description Figure 14.
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Pinouts and pin description STM32F401xD STM32F401xE Table 7.
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STM32F401xD STM32F401xE Pinouts and pin description WLCSP49 LQFP64 LQFP100 UFBGA100 3 C7 3 8 D1 PC14OSC32_IN (PC14) I/O FT 4 C6 4 9 E1 PC15OSC32_OUT (PC15) I/O FT - - - 10 F2 VSS S - - - - - - - 11 G2 VDD S - - - - 5 D7 5 12 F1 PH0-OSC_IN (PH0) I/O FT (4) EVENTOUT OSC_IN 6 D6 6 13 G1 PH1OSC_OUT (PH1) I/O FT (4) EVENTOUT OSC_OUT 7 E7 7 14 H2 NRST I/O FT - EVENTOUT - - - 8 15 H1 PC0 I/O FT - EVENTOUT ADC1_IN10 - - 9 16 J2 P
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Pinouts and pin description STM32F401xD STM32F401xE WLCSP49 LQFP64 LQFP100 UFBGA100 Pin name (function after reset)(1) 13 E4 17 26 L3 PA3 - - 18 27 - VSS S - - - - - - 19 28 - VDD S - - - - - - - - E3 BYPASS_ REG I FT - - - I/O FT Notes UQFN48 Pin type Pin Number I/O structure Table 8.
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STM32F401xD STM32F401xE Pinouts and pin description WLCSP49 LQFP64 LQFP100 UFBGA100 Pin name (function after reset)(1) - - - 45 M11 PE14 I/O FT - SPI4_MOSI, TIM1_CH4, EVENTOUT - - - - 46 M12 PE15 I/O FT - TIM1_BKIN, EVENTOUT - 21 E3 29 47 L10 PB10 I/O FT - SPI2_SCK/I2S2_CK, I2C2_SCL, TIM2_CH3, EVENTOUT - - - - - K9 PB11 I/O FT - EVENTOUT - Notes UQFN48 Pin type Pin Number I/O structure Table 8.
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Pinouts and pin description STM32F401xD STM32F401xE WLCSP49 LQFP64 LQFP100 UFBGA100 Pin name (function after reset)(1) - - 39 65 E10 PC8 I/O FT - USART6_CK, TIM3_CH3, SDIO_D0, EVENTOUT - - - 40 66 D12 PC9 I/O FT - I2S_CKIN, I2C3_SDA, TIM3_CH4, SDIO_D1, MCO_2, EVENTOUT - 29 D1 41 67 D11 PA8 I/O FT - I2C3_SCL, USART1_CK, TIM1_CH1, OTG_FS_SOF, MCO_1, EVENTOUT - 30 D2 42 68 D10 PA9 I/O FT - I2C3_SMBA, USART1_TX, TIM1_CH2, EVENTOUT OTG_FS_VBUS 31 C2 43 69 C12 P
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STM32F401xD STM32F401xE Pinouts and pin description WLCSP49 LQFP64 LQFP100 UFBGA100 Pin name (function after reset)(1) - - - 82 B9 PD1 I/O FT - EVENTOUT - - - 54 83 C8 PD2 I/O FT - TIM3_ETR, SDIO_CMD, EVENTOUT - - - - 84 B8 PD3 I/O FT - SPI2_SCK/I2S2_CK, USART2_CTS, EVENTOUT - - - - 85 B7 PD4 I/O FT - USART2_RTS, EVENTOUT - - - - 86 A6 PD5 I/O FT - USART2_TX, EVENTOUT - - - - 87 B6 PD6 I/O FT - SPI3_MOSI/I2S3_SD, USART2_RX, EVENTOUT - - -
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Pinouts and pin description STM32F401xD STM32F401xE Table 8. STM32F401xD/xE pin definitions (continued) UQFN48 WLCSP49 LQFP64 LQFP100 UFBGA100 Pin name (function after reset)(1) Pin type I/O structure Notes Pin Number Alternate functions 47 A6 63 99 - VSS S - - - - - B6 - - H3 PDR_ON I FT - - - 48 A7 - VDD S - - - - 64 100 Additional functions 1. Function availability depends on the chosen device. 2. PC13, PC14 and PC15 are supplied through the power switch.
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Downloaded from Arrow.com. - - PH1 SYS_AF PH0 Port AF00 - - TIM1/TIM2 AF01 - - TIM3/ TIM4/ TIM5 AF02 - - TIM9/ TIM10/ TIM11 AF03 - - I2C1/I2C2/ I2C3 AF04 - - SPI1/SPI2/ I2S2/SPI3/ I2S3/SPI4 AF05 - - SPI2/I2S2/ SPI3/ I2S3 AF06 - - SPI3/I2S3/ USART1/ USART2 AF07 - - USART6 AF08 Table 9.
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STM32F401xD STM32F401xE 5 Memory mapping Memory mapping The memory map is shown in Figure 15. Figure 15. Memory map 5HVHUYHG [( [)))) )))) &RUWH[ 0 LQWHUQDO SHULSKHUDOV [( [( ) )))) ['))) )))) 5HVHUYHG [ [ )))) $+% 5HVHUYHG [)))) )))) [( ['))) )))) 0E\WH EORFN &RUWH[ 0 V LQWHUQDO SHULSKHUDOV [ [ [ ))) )))) [ )) $+% 0E\WH EORFN 1RW XVHG [& [%))) )))) [ 5HVHUYHG [ &
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Memory mapping STM32F401xD STM32F401xE Table 10. STM32F401xD register boundary addresses Bus ® Cortex -M4 AHB2 AHB1 52/135 Downloaded from Arrow.com.
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STM32F401xD STM32F401xE Memory mapping Table 10.
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Memory mapping STM32F401xD STM32F401xE Table 10. STM32F401xD register boundary addresses (continued) Bus APB1 54/135 Downloaded from Arrow.com.
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STM32F401xD STM32F401xE Electrical characteristics 6 Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range).
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Electrical characteristics 6.1.5 STM32F401xD STM32F401xE Pin input voltage The input voltage measurement on a pin of the device is described in Figure 17. Figure 17. Input voltage measurement -#5 PIN 6). -3 6 56/135 Downloaded from Arrow.com.
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STM32F401xD STM32F401xE 6.1.6 Electrical characteristics Power supply scheme Figure 18. Power supply scheme 9%$7 9%$7 WR 9 *3,2V ,1 9&$3B 9&$3B 9'' 966 î Q) î ) /HYHO VKLIWHU 287 î ) RU î ) 9'' %DFNXS FLUFXLWU\ 26& . 57& :DNHXS ORJLF %DFNXS UHJLVWHUV 3RZHU VZLWFK ,2 /RJLF .HUQHO ORJLF &38 GLJLWDO 5$0 9ROWDJH UHJXODWRU )ODVK PHPRU\ %<3$66B5(* 3'5B21 9'' 9''$ 95() Q) ) 5HVHW FRQWUROOHU Q) ) 95()
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Electrical characteristics 6.1.7 STM32F401xD STM32F401xE Current consumption measurement Figure 19. Current consumption measurement scheme )$$?6"!4 6"!4 )$$ 6$$ 6$$! AI 6.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 11: Voltage characteristics, Table 12: Current characteristics, and Table 13: Thermal characteristics may cause permanent damage to the device.
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STM32F401xD STM32F401xE Electrical characteristics Table 12. Current characteristics Symbol Ratings Max.
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Electrical characteristics STM32F401xD STM32F401xE 6.3 Operating conditions 6.3.1 General operating conditions Table 14.
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STM32F401xD STM32F401xE Electrical characteristics Table 14. General operating conditions (continued) Symbol Parameter Conditions Typ Max Ambient temperature for 6 suffix version Maximum power dissipation –40 - 85 Low power dissipation(8) –40 - 105 Ambient temperature for 7 suffix version Maximum power dissipation –40 - 105 Low power dissipation –40 - 125 6 suffix version –40 - 105 7 suffix version –40 - 125 TA TJ Min Junction temperature range (8) Unit °C 1.
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Electrical characteristics STM32F401xD STM32F401xE 1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no wait state is required. 2. Thanks to the ART accelerator and the 128-bit Flash memory, the number of wait states given here does not impact the execution speed from Flash memory since the ART accelerator allows to achieve a performance equivalent to 0 wait state program execution. 3. Refer to for frequencies vs. external load. 4.
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STM32F401xD STM32F401xE 6.3.3 Electrical characteristics Operating conditions at power-up/power-down (regulator ON) Subject to general operating conditions for TA. Table 17. Operating conditions at power-up / power-down (regulator ON) Symbol tVDD 6.3.4 Parameter Min Max VDD rise time rate 20 ∞ VDD fall time rate 20 ∞ Unit µs/V Operating conditions at power-up / power-down (regulator OFF) Subject to general operating conditions for TA. Table 18.
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Electrical characteristics 6.3.5 STM32F401xD STM32F401xE Embedded reset and power control block characteristics The parameters given in Table 19 are derived from tests performed under ambient temperature and VDD supply voltage @ 3.3V. Table 19. Embedded reset and power control block characteristics Symbol VPVD Parameter Programmable voltage detector level selection Conditions Min Typ Max PLS[2:0]=000 (rising edge) 2.09 2.14 2.19 PLS[2:0]=000 (falling edge) 1.98 2.04 2.
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STM32F401xD STM32F401xE Electrical characteristics Table 19. Embedded reset and power control block characteristics (continued) Symbol Parameter IRUSH(2) ERUSH (2) Conditions Min Typ Max Unit InRush current on voltage regulator poweron (POR or wakeup from Standby) - 160 200 mA InRush energy on voltage regulator power- VDD = 1.7 V, TA = 105 °C, on (POR or wakeup from IRUSH = 171 mA for 31 µs Standby) - - 5.4 µC 1.
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Electrical characteristics STM32F401xD STM32F401xE Table 20. Typical and maximum current consumption, code with data processing (ART accelerator disabled) running from SRAM - VDD = 1.7 V Max(1) Typ Symbol Parameter Conditions External clock, all peripherals enabled(2)(3) IDD Supply current in Run mode External clock, all peripherals disabled(3) fHCLK (MHz) Unit TA= 25 °C TA= 25 °C TA=85 °C TA=105 °C 84 21.8 23.1 24.1 25.3(4) 60 15.8 16.5 17.5 18.7 40 11.4 11.9 12.9 13.9 20 6.
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STM32F401xD STM32F401xE Electrical characteristics Table 22. Typical and maximum current consumption in run mode, code with data processing (ART accelerator enabled except prefetch) running from Flash memory- VDD = 1.7 V Symbol Parameter Conditions External clock, all peripherals enabled(2)(3) IDD Supply current in Run mode External clock, all peripherals disabled(3) Max(1) fHCLK (MHz) Typ TA = 25 °C TA = 85 °C TA = 105 °C 84 23.2 24.5 25.6 26.6 60 15.1 16.3 17.4 18.4 40 10.8 12.
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Electrical characteristics STM32F401xD STM32F401xE . Table 24. Typical and maximum current consumption in run mode, code with data processing (ART accelerator disabled) running from Flash memory Symbol Parameter Conditions External clock, all peripherals enabled(2)(3) IDD Supply current in Run mode External clock, all peripherals disabled(3) Max(1) fHCLK (MHz) Typ TA = 25 °C TA = 85 °C TA = 105 °C 84 31.1 32.2 34.3 36.3 60 21.7 22.1 23.2 24.2 40 15.5 16.1 17.1 18.1 30 12.6 13.
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STM32F401xD STM32F401xE Electrical characteristics Table 26. Typical and maximum current consumption in Sleep mode Symbol Parameter Conditions External clock, all peripherals enabled(2)(3) IDD Supply current in Sleep mode External clock, all peripherals disabled(3)(4) Max(1) fHCLK (MHz) Typ TA = 25 °C TA = 85 °C TA = 105 °C 84 16.6 17.4 18.4 19.5 60 10.8 11.2 12.3 13.3 40 8.3 9.0 10.0 11.0 30 6.8 7.1 8.1 9.1 20 5.9 6.1 7.1 8.1 84 5.3 6.1 7.1 8.2 60 3.7 4.1 5.
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Electrical characteristics STM32F401xD STM32F401xE Table 28. Typical and maximum current consumption in Stop mode - VDD=3.
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STM32F401xD STM32F401xE Electrical characteristics Table 31. Typical and maximum current consumptions in VBAT mode Max(2) Typ Symbol TA = 85 °C TA = 25 °C Conditions(1) Parameter VBAT = VBAT= VBAT = 1.7 V 2.4 V 3.3 V Backup Low-speed oscillator (LSE) and RTC ON IDD_VBAT domain supply RTC and LSE OFF current TA = 105 °C Unit VBAT = 3.6 V 0.66 0.76 0.97 3.0 5.0 0.1 0.1 0.1 2.0 4.0 µA 1. Crystal used: Abracon ABS07-120-32.768 kHz-T with a CL of 6 pF for typical values. 2.
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Electrical characteristics STM32F401xD STM32F401xE required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs. Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise.
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STM32F401xD STM32F401xE Electrical characteristics Table 32. Switching output I/O current consumption Symbol Parameter Conditions(1) VDD = 3.3 V C = CINT VDD = 3.3 V CEXT = 0 pF C = CINT + CEXT + CS IDDIO I/O switching current VDD = 3.3 V CEXT =10 pF C = CINT + CEXT + CS VDD = 3.3 V CEXT = 22 pF C = CINT + CEXT + CS VDD = 3.3 V CEXT = 33 pF C = CINT + CEXT + CS I/O toggling frequency (fSW) Typ 2 MHz 0.05 8 MHz 0.15 25 MHz 0.45 50 MHz 0.85 60 MHz 1.00 84 MHz 1.40 2 MHz 0.
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Electrical characteristics STM32F401xD STM32F401xE On-chip peripheral current consumption The MCU is placed under the following conditions: • At startup, all I/O pins are in analog input configuration. • All peripherals are disabled unless otherwise mentioned. • The ART accelerator is ON. • Voltage Scale 2 mode selected, internal digital voltage V12 = 1.26 V. • HCLK is the system clock at 84 MHz. fPCLK1 = fHCLK/2, and fPCLK2 = fHCLK.
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STM32F401xD STM32F401xE Electrical characteristics Table 33. Peripheral current consumption (continued) Peripheral IDD (typ) TIM1 5.71 TIM9 2.86 TIM10 1.79 TIM11 2.02 (2) ADC1 2.98 SPI1 1.19 USART1 3.10 USART6 2.86 SDIO 5.95 SPI4 1.31 SYSCFG 0.71 APB2 (up to 84MHz) Unit µA/MHz 1. I2SMOD bit set in SPI_I2SCFGR register, and then the I2SE bit set to enable I2S peripheral. 2. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.
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Electrical characteristics 6.3.8 STM32F401xD STM32F401xE External clock source characteristics High-speed external user clock generated from an external source In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O. The external clock signal has to respect the Table 54. However, the recommended clock input waveform is shown in Figure 22.
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STM32F401xD STM32F401xE Electrical characteristics Table 36. Low-speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit - 32.768 1000 kHz 0.7VDD - VDD fLSE_ext User External clock source frequency(1) VLSEH OSC32_IN input pin high level voltage VLSEL OSC32_IN input pin low level voltage VSS - 0.
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Electrical characteristics STM32F401xD STM32F401xE Figure 23. Low-speed external clock source AC timing diagram 6,3%( 6,3%, TR ,3% TF ,3% T7 ,3% T7 ,3% T 4,3% F,3%?EXT %XTERNAL CLOCK SOURCE ), /3# ?). 34- & AI High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 26 MHz crystal/ceramic resonator oscillator.
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STM32F401xD STM32F401xE Electrical characteristics series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com. Figure 24.
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Electrical characteristics STM32F401xD STM32F401xE Figure 25. Typical application with a 32.768 kHz crystal 5HVRQDWRU ZLWK LQWHJUDWHG FDSDFLWRUV &/ I/6( 26& B,1 %LDV 5) FRQWUROOHG JDLQ N+ ] UHVRQDWRU 26& B28 7 &/ 670 ) DL 6.3.9 Internal clock source characteristics The parameters given in Table 39 and Table 40 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 14. High-speed internal (HSI) RC oscillator Table 39.
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STM32F401xD STM32F401xE Electrical characteristics Figure 26. ACCHSI versus temperature !##(3) 4! # -IN -AX 4YPICAL -3 6 1. Guaranteed by characterization, not tested in production. Low-speed internal (LSI) RC oscillator Table 40.
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Electrical characteristics STM32F401xD STM32F401xE Figure 27. ACCLSI versus temperature MAX AVG MIN .ORMALIZED DEVIATI ON 4EMPERAT URE # -3 6 6.3.10 PLL characteristics The parameters given in Table 41 and Table 42 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 14. Table 41.
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STM32F401xD STM32F401xE Electrical characteristics Table 41. Main PLL characteristics (continued) Symbol Parameter Conditions Min Typ Max IDD(PLL)(4) PLL power consumption on VDD VCO freq = 192 MHz VCO freq = 432 MHz 0.15 0.45 - 0.40 0.75 IDDA(PLL)(4) PLL power consumption on VDDA VCO freq = 192 MHz VCO freq = 432 MHz 0.30 0.55 - 0.40 0.85 Unit mA 1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values.
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Electrical characteristics 6.3.11 STM32F401xD STM32F401xE PLL spread spectrum clock generation (SSCG) characteristics The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic interferences(see Table 49: EMI characteristics for WLCSP49). It is available only on the main PLL. Table 43. SSCG parameters constraint Symbol Parameter Min Typ Max(1) Unit fMod Modulation frequency - - 10 KHz md Peak modulation depth 0.25 - 2 % - 215 MODEPER * INCSTEP - -1 - 1.
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STM32F401xD STM32F401xE Electrical characteristics Figure 28 and Figure 29 show the main PLL output clock waveforms in center spread and down spread modes, where: F0 is fPLL_OUT nominal. Tmode is the modulation period. md is the modulation depth. Figure 28. PLL output clock waveforms in center spread mode &REQUENCY 0,,?/54 MD & MD TMODE 4IME XTMODE AI Figure 29. PLL output clock waveforms in down spread mode &REQUENCY 0,,?/54 & XMD TMODE 4IME XTMODE AI 6.3.
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Electrical characteristics STM32F401xD STM32F401xE Table 45.
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STM32F401xD STM32F401xE Electrical characteristics Table 46. Flash memory programming with VPP voltage (continued) Symbol Parameter Conditions Min(1) Typ Max(1) Unit 2.7 - 3.6 V Vprog Programming voltage VPP VPP voltage range 7 - 9 V IPP Minimum current sunk on the VPP pin 10 - - mA - - 1 hour tVPP(3) Cumulative time during which VPP is applied 1. Guaranteed by design, not tested in production. 2. The maximum programming time is measured after 100K erase operations. 3.
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Electrical characteristics STM32F401xD STM32F401xE Table 48. EMS characteristics for LQFP100 package Symbol Parameter Conditions Level/ Class VFESD Voltage limits to be applied on any I/O pin to induce a functional disturbance VDD = 3.3 V, LQFP100, WLCSP49, TA = +25 °C, fHCLK = 84 MHz, conforms to IEC 61000-4-2 2B VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD = 3.
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STM32F401xD STM32F401xE Electrical characteristics Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application, executing EEMBC code, is running. This emission test is compliant with SAE IEC61967-2 standard which specifies the test board and the pin loading. Table 49. EMI characteristics for WLCSP49 Symbol Parameter Conditions Monitored frequency band Max vs. [fHSE/fCPU] Unit 8/84 MHz SEMI Peak level VDD = 3.
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Electrical characteristics STM32F401xD STM32F401xE Table 51. ESD absolute maximum ratings Symbol Ratings Conditions Class Maximum value(1) VESD(HBM) Electrostatic discharge TA = +25 °C conforming to JESD22voltage (human body model) A114 2 2000 VESD(CDM) Electrostatic discharge voltage (charge device model) II 400 TA = +25 °C conforming to ANSI/ESD STM5.3.1 Unit V 1. Guaranteed by characterization, not tested in production.
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STM32F401xD STM32F401xE Electrical characteristics Table 53.
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Electrical characteristics STM32F401xD STM32F401xE Table 54. I/O static characteristics (continued) Symbol Parameter FT and NRST I/O input hysteresis BOOT0 I/O input hysteresis RPU RPD CIO(8) Min Typ Max Unit 1.7 V≤ VDD≤ 3.6 V - 10% VDD(3) - V - 100 - mV VSS ≤ VIN ≤ VDD - - ±1 VIN = 5 V - - 3 30 40 50 7 10 14 1.75 V≤ VDD ≤ 3.6 V, -40 °C≤ TA ≤ 105 °C VHYS Ilkg Conditions 1.7 V≤ VDD ≤ 3.
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STM32F401xD STM32F401xE Electrical characteristics Figure 30.
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Electrical characteristics STM32F401xD STM32F401xE Table 55.
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STM32F401xD STM32F401xE Electrical characteristics Table 56.
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Electrical characteristics STM32F401xD STM32F401xE Figure 31. I/O AC characteristics definition (;7(51$/ 287387 21 &/ WU ,2 RXW WI ,2 RXW 7 0D[LPXP IUHTXHQF\ LV DFKLHYHG LI WU WI 7 DQG LI WKH GXW\ F\FOH LV ZKHQ ORDGHG E\ &/ VSHFLILHG LQ WKH WDEOH ³ , 2 $& FKDUDFWHULVWLFV´ 6.3.17 DL G NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 54).
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STM32F401xD STM32F401xE Electrical characteristics Figure 32. Recommended NRST pin protection 9'' ([WHUQDO UHVHW FLUFXLW 1567 538 ,QWHUQDO 5HVHW )LOWHU ) 670 ) DL F 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 57. Otherwise the reset is not taken into account by the device. 6.3.
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Electrical characteristics 6.3.19 STM32F401xD STM32F401xE Communications interfaces I2C interface characteristics The I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” opendrain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The I2C characteristics are described in Table59. Refer also to Section 6.3.
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STM32F401xD STM32F401xE Electrical characteristics Figure 33. I2C bus AC waveforms and measurement circuit s ''B, & s ''B, & 53 53 670 )[[ 56 6'$ ,ð& EXV 56 6&/ 67$57 5(3($7(' 67$57 67$57 WVX 67$ 6'$ WI 6'$ WU 6'$ WK 67$ WVX 6'$ WZ 672 67$ 6723 WK 6'$ WZ 6&/+ 6&/ WU 6&/ WZ 6&// WI 6&/ WVX 672 DL F 1. RS = series protection resistor. 2. RP = external pull-up resistor. 3. VDD_I2C is the I2C bus power supply. Table 60. SCL frequency (fPCLK1= 42 MHz, VDD = VDD_I2C = 3.
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Electrical characteristics STM32F401xD STM32F401xE SPI interface characteristics Unless otherwise specified, the parameters given in Table 61 for the SPI interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 14, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5VDD Refer to Section 6.3.
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STM32F401xD STM32F401xE Electrical characteristics Table 61. SPI dynamic characteristics(1) (continued) Symbol Parameter tv(MO) Data output valid time th(MO) Conditions Data output hold time Min Typ Max Unit Master mode (after enable edge) - 3 5 ns Master mode (after enable edge) 2 - - ns 1. Guaranteed by characterization, not tested in production. 2.
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Electrical characteristics STM32F401xD STM32F401xE Figure 36. SPI timing diagram - master mode(1) High NSS input SCK Input CPHA= 0 CPOL=0 SCK Input tc(SCK) CPHA=1 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=1 tsu(MI) MISO INP UT tw(SCKH) tw(SCKL) MS BIN tr(SCK) tf(SCK) BI T6 IN LSB IN th(MI) MOSI OUTPUT M SB OUT tv(MO) B I T1 OUT LSB OUT th(MO) ai14136 102/135 Downloaded from Arrow.com.
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STM32F401xD STM32F401xE Electrical characteristics I2S interface characteristics Unless otherwise specified, the parameters given in Table 62 for the I2S interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 14, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5VDD Refer to Section 6.3.
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Electrical characteristics STM32F401xD STM32F401xE Figure 37. I2S slave timing diagram (Philips protocol)(1) tc(CK) CK Input CPOL = 0 CPOL = 1 tw(CKH) th(WS) tw(CKL) WS input tv(SD_ST) tsu(WS) SDtransmit LSB transmit(2) MSB transmit Bitn transmit tsu(SD_SR) LSB receive(2) SDreceive th(SD_ST) LSB transmit th(SD_SR) MSB receive Bitn receive LSB receive ai14881b 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 38.
PAGE 105
STM32F401xD STM32F401xE Electrical characteristics USB OTG full speed (FS) characteristics This interface is present in USB OTG FS controller. Table 63. USB OTG FS startup time Symbol tSTARTUP(1) Parameter USB OTG FS transceiver startup time Max Unit 1 µs 1. Guaranteed by design, not tested in production. Table 64. USB OTG FS DC electrical characteristics Symbol VDD Input levels Parameter Conditions USB OTG FS operating voltage Min.(1) Typ. Max.(1) Unit 3.0(2) - 3.
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Electrical characteristics STM32F401xD STM32F401xE Figure 39. USB OTG FS timings: definition of data signal rise and fall time Crossover points Differen tial Data L ines VCRS VS S tr tf ai14137 Table 65. USB OTG FS electrical characteristics(1) Driver characteristics Symbol Parameter Rise time(2) tr tf Fall trfm time(2) Conditions Min Max Unit CL = 50 pF 4 20 ns CL = 50 pF 4 20 ns tr/tf 90 110 % 1.3 2.0 V Rise/ fall time matching VCRS Output signal crossover voltage 1.
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STM32F401xD STM32F401xE Electrical characteristics Table 66. ADC characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit - - 0.100 µs - - 3(5) 1/fADC - - 0.067 µs - - 2(5) 1/fADC 0.100 - 16 µs 3 - 480 1/fADC - 2 3 µs fADC = 30 MHz 12-bit resolution 0.50 - 16.40 µs fADC = 30 MHz 10-bit resolution 0.43 - 16.34 µs fADC = 30 MHz 8-bit resolution 0.37 - 16.27 µs fADC = 30 MHz 6-bit resolution 0.30 - 16.
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Electrical characteristics STM32F401xD STM32F401xE The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of sampling periods defined in the ADC_SMPR1 register. Table 67. ADC accuracy at fADC = 18 MHz(1) Symbol Parameter ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error Test conditions fADC =18 MHz VDDA = 1.
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STM32F401xD STM32F401xE Electrical characteristics Table 70. ADC dynamic accuracy at fADC = 18 MHz - limited test conditions(1) Symbol Parameter Test conditions ENOB Effective number of bits SINAD Signal-to-noise and distortion ratio SNR Signal-to-noise ratio THD Total harmonic distortion fADC =18 MHz VDDA = VREF+= 1.7 V Input Frequency = 20 KHz Temperature = 25 °C Min Typ Max Unit 10.3 10.4 - bits 64 64.2 - 64 65 - -67 -72 - dB 1.
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Electrical characteristics STM32F401xD STM32F401xE Figure 40. ADC accuracy characteristics ; ,3" )$%!, 6 2%& OR 6 $$! DEPENDING ON PACKAGE = %' %4 %/ %, %$ , 3")$%!, 6 33! 6$$! AI C 1. See also Table 68. 2. Example of an actual transfer curve. 3. Ideal transfer curve. 4. End point correlation line. 5.
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STM32F401xD STM32F401xE Electrical characteristics General PCB design guidelines Power supply decoupling should be performed as shown in Figure 42 or Figure 43, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 42.
PAGE 112
Electrical characteristics 6.3.21 STM32F401xD STM32F401xE Temperature sensor characteristics Table 72. Temperature sensor characteristics Symbol Parameter Min Typ Max Unit VSENSE linearity with temperature - ±1 ±2 °C Average slope - 2.5 - mV/°C Voltage at 25 °C - 0.76 - V tSTART(2) Startup time - 6 10 µs TS_temp(2) ADC sampling time when reading the temperature (1 °C accuracy) 10 - - µs TL(1) Avg_Slope (1) V25(1) 1.
PAGE 113
STM32F401xD STM32F401xE Electrical characteristics Table 75. Embedded internal reference voltage (continued) Symbol Parameter TCoeff(2) tSTART (2) Conditions Min Typ Max Unit Temperature coefficient - - 30 50 ppm/°C Startup time - - 6 10 µs 1. Shortest sampling time can be determined in the application by multiple iterations. 2. Guaranteed by design, not tested in production Table 76. Internal reference voltage calibration values 6.3.
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Electrical characteristics STM32F401xD STM32F401xE Figure 45. SD default mode CK tOVD tOHD D, CMD (output) ai14888 Table 77. Dynamic characteristics: SD / MMC characteristics(1)(2) Symbol Parameter fPP Conditions Min Typ Max Unit Clock frequency in data transfer mode 0 - 48 MHz - SDIO_CK/fPCLK2 frequency ratio - - 8/3 - tW(CKL) Clock low time fpp = 48MHz 8.5 9 - tW(CKH) Clock high time fpp = 48MHz 8.
PAGE 115
STM32F401xD STM32F401xE Package characteristics 7 Package characteristics 7.1 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DocID025644 Rev 3 115/135 133 Downloaded from Arrow.com.
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Package characteristics 7.1.1 STM32F401xD STM32F401xE WLCSP49, 3.06 x 3.06 mm, 0.4 mm pitch wafer level chip size package Figure 46. WLCSP49 wafer level chip size package outline E & ! BALL LOCATION ! ' $ETAIL ! E % E ' ! ! E "UMP SIDE 3IDE VIEW ! &RONT VIEW "UMP $ ! EEE : B 3EATING PLANE .OTE % ! ORIENTATION REFERENCE $ETAIL ! ROTATED .OTE 7AFER BACK SIDE ! 8-?-%?6 1. Drawing is not to scale. Table 79.
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STM32F401xD STM32F401xE Package characteristics Table 79. STM32F401xCE WLCSP49 wafer level chip size package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A2 - 0.380 - - 0.0150 - A3(2) - 0.025 - - 0.0010 - (3) 0.220 0.250 0.280 0.0087 0.0098 0.0110 D 2.994 3.029 3.064 0.1179 0.1193 0.1206 E 2.994 3.029 3.064 0.1179 0.1193 0.1206 e - 0.400 - - 0.0157 - e1 - 2.400 - - 0.0945 - e2 - 2.400 - - 0.0945 - F - 0.3145 - - 0.
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Package characteristics STM32F401xD STM32F401xE Table 80. WLCSP49 recommended PCB design rules (0.4 mm pitch) Dimension Recommended values Pitch 0.4 mm Dpad 260 µm max. (circular) 220 µm recommended Dsm 300 µm min. (for 260 µm diameter pad) PCB pad design Non-solder mask defined via underbump allowed Device marking Figure 48. Example of WLCSP49 marking (top view) %DOO LQGHQWLILHU 3URGXFW LGHQWLILFDWLRQ ) &' 5HYLVLRQ FRGH 'DWH FRGH < :: 5 06Y 9 1.
PAGE 119
STM32F401xD STM32F401xE 7.1.2 Package characteristics UFQFPN48, 7 x 7 mm, 0.5 mm pitch package Figure 49. UFQFPN48, 7 x 7 mm, 0.5 mm pitch, package outline 3LQ LGHQWLILHU ODVHU PDUNLQJ DUHD ' $ ( ( 7 GGG 6HDWLQJ SODQH $ E H 'HWDLO < ' ([SRVHG SDG DUHD < ' / & [ SLQ FRUQHU 5 W\S 'HWDLO = ( = $ % B0(B9 1. Drawing is not to scale. 2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life. 3.
PAGE 120
Package characteristics STM32F401xD STM32F401xE Table 81. UFQFPN48, 7 x 7 mm, 0.5 mm pitch, package mechanical data (continued) inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. T - 0.152 - - 0.0060 - b 0.200 0.250 0.300 0.0079 0.0098 0.0118 e - 0.500 - - 0.0197 - 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 50.
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STM32F401xD STM32F401xE Package characteristics Device marking Figure 51. Example of UFQFPN48 marking (top view) 3URGXFW LGHQWLILFDWLRQ 670 ) &'8 'DWH FRGH < :: 3LQ LQGHQWLILHU 5HYLVLRQ FRGH 5 06Y 9 1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge.
PAGE 122
Package characteristics 7.1.3 STM32F401xD STM32F401xE LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package Figure 52. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package outline PP *$8*( 3/$1( F $ $ $ 6($7,1* 3/$1( & $ FFF & ' ' ' . / / 3,1 ,'(17,),&$7,21 ( ( ( E H :B0(B9 1. Drawing is not to scale. 122/135 Downloaded from Arrow.com.
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STM32F401xD STM32F401xE Package characteristics Table 82. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. A - - 1.60 - - 0.0630 A1 0.05 - 0.15 0.0020 - 0.0059 A2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 - 0.20 0.0035 - 0.0079 D - 12.00 - - 0.4724 - D1 - 10.00 - - 0.3937 - E - 12.00 - - 0.4724 - E1 - 10.00 - - 0.
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Package characteristics STM32F401xD STM32F401xE Device marking Figure 54. Example of LQFP64 marking (top view) 5HYLVLRQ FRGH 3URGXFW LGHQWLILFDWLRQ 5 670 ) 5'7 'DWH FRGH < :: 3LQ LQGHQWLILHU 06Y 9 1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge.
PAGE 125
STM32F401xD STM32F401xE 7.1.4 Package characteristics LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package Figure 55. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package outline MM C ! ! ! 3%!4).' 0,!.% # '!5'% 0,!.% $ , $ ! + CCC # , $ 0). )$%.4)&)#!4)/. % % % B E ,?-%?6 1. Drawing is not to scale. DocID025644 Rev 3 125/135 133 Downloaded from Arrow.com.
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Package characteristics STM32F401xD STM32F401xE Table 83. LQPF100, 14 x 14 mm, 100-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. A - - 1.6 - - 0.063 A1 0.05 - 0.15 0.002 - 0.0059 A2 1.35 1.4 1.45 0.0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 - 0.2 0.0035 - 0.0079 D 15.8 16 16.2 0.622 0.6299 0.6378 D1 13.8 14 14.2 0.5433 0.5512 0.5591 D3 - 12 - - 0.4724 - E 15.
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STM32F401xD STM32F401xE Package characteristics Figure 56. LQFP100 recommended footprint AI C 1. Dimensions are in millimeters. Device marking Figure 57. Example of LQPF100 marking (top view) 3URGXFW LGHQWLILFDWLRQ (6 ) 2SWLRQDO JDWH PDUN 9'7 5 5HYLVLRQ FRGH 'DWH FRGH < :: 3LQ LQGHQWLILHU 06Y 9 1.
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Package characteristics 7.1.5 STM32F401xD STM32F401xE UFBGA100, 7 x 7 mm, 0.5 mm pitch package Figure 58. UFBGA100, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package outline = 6HDWLQJ SODQH GGG = $ $ $ $ $ ( H $ EDOO $ EDOO LGHQWLILHU LQGH[ DUHD ) ; ( $ ) ' ' H < 0 %27720 9,(: E EDOOV HHH 0 = < ; III 0 = 723 9,(: $ & B0(B9 1. Drawing is not to scale. Table 84. UFBGA100, 7 x 7 mm, 0.
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STM32F401xD STM32F401xE Package characteristics Table 84. UFBGA100, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. ddd - - 0.100 - - 0.0039 eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 59. Recommended PCB design rules for pads (0.5 mm-pitch BGA) Pitch 0.5 mm D pad 0.27 mm Dsm 0.
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Package characteristics STM32F401xD STM32F401xE Device marking Figure 60. Example of UFBGA100 marking (top view) 3URGXFW LGHQWLILFDWLRQ 670 ) 9(+ 'DWH FRGH < :: %DOO LQGHQWLILHU 5HYLVLRQ FRGH 5 06Y 9 1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge.
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STM32F401xD STM32F401xE 7.2 Package characteristics Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 14: General operating conditions on page 60. The maximum chip-junction temperature, TJ max.
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Part numbering 8 STM32F401xD STM32F401xE Part numbering Table 86.
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STM32F401xD STM32F401xE Part numbering Table 87. Device order codes Reference Order codes STM32F401xD STM32F401CDY6, STM32F401RDT6, STM32F401VDT6, STM32F401CDU6, STM32F401VDH6 STM32F401xE STM32F401CEY6, STM32F401RET6, STM32F401VET6, STM32F401CEU6, STM32F401VEH6 DocID025644 Rev 3 133/135 133 Downloaded from Arrow.com.
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Revision history 9 STM32F401xD STM32F401xE Revision history Table 88. Document revision history Date Revision 16-Jan-2014 1 Initial release. 2 Updated Flash memory size in Table 2: STM32F401xD/xE features and peripheral counts. Added alternate functions mapped on PCx, PDx and PEx GPIOS in Table 9: Alternate function mapping 3 Updated UFQFPN48 in Table 3: Regulator ON/OFF and internal power supply supervisor availability. Updated number of EXTI lines in Section 3.
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STM32F401xD STM32F401xE IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.