Datasheet

DS9716 Rev 11 137/139
STM32F401xB STM32F401xC Revision history
138
28-Apr-2017 7
Updated:
– Features
– Section 2: Description
– Table 2: STM32F401xB/C features and peripheral counts
– Table 13: Thermal characteristics
– Table 14: General operating conditions
– Table 19: Embedded reset and power control block characteristics
– Table 20: Typical and maximum current consumption, code with data
processing (ART accelerator disabled) running from SRAM - VDD
=1.8V
– Table 21: Typical and maximum current consumption, code with data
processing (ART accelerator disabled) running from SRAM
– Table 22: Typical and maximum current consumption in run mode,
code with data processing (ART accelerator enabled except
prefetch) running from Flash memory- VDD = 1.8 V
– Table 24: Typical and maximum current consumption in run mode,
code with data processing (ART accelerator disabled) running from
Flash memory
– Table 25: Typical and maximum current consumption in run mode,
code with data processing (ART accelerator enabled with prefetch)
running from Flash memory
– Table 26: Typical and maximum current consumption in Sleep mode
– Table 27: Typical and maximum current consumptions in Stop mode
- VDD = 1.8 V
– Table 28: Typical and maximum current consumption in Stop mode -
VDD=3.3 V
– Table 29: Typical and maximum current consumption in Standby
mode - VDD= 1.8 V
– Table 30: Typical and maximum current consumption in Standby
mode - VDD=3.3 V
– Table 31: Typical and maximum current consumptions in VBAT mode
– Table 39: HSI oscillator characteristics
– Table 47: Flash memory endurance and data retention
– Table 54: I/O static characteristics
– Figure 32: Recommended NRST pin protection
– Figure 58: UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine
pitch ball grid array package outline
– Table 84: UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine
pitch ball grid array package mechanical data
– Table 87: Ordering information scheme
Table 87. Document revision history (continued)
Date Revision Changes
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