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This is information on a product in full production.

April 2019 DS9716 Rev 11 1/139

STM32F401xB STM32F401xC

Arm

Cortex

-M4 32-bit MCU+FPU, 105 DMIPS,

256KB Flash / 64KB RAM, 11 TIMs, 1 ADC, 11 comm. interfaces

Datasheet - production data

Features

• Dynamic efficiency line with BAM (batch

acquisition mode)

– 1.7 V to 3.6 V power supply

– -40 °C to 85/105/125 °C temperature range

• Core: Arm

32-bit Cortex

-M4 CPU with FPU,

Adaptive real-time accelerator (ART

Accelerator™) allowing 0-wait state execution

from Flash memory, frequency up to 84 MHz,

memory protection unit, 105 DMIPS/

1.25 DMIPS/MHz (Dhrystone 2.1), and DSP

instructions

• Memories

– Up to 256 Kbytes of Flash memory

– 512 bytes of OTP memory

– Up to 64 Kbytes of SRAM

• Clock, reset and supply management

– 1.7 V to 3.6 V application supply and I/Os

– POR, PDR, PVD and BOR

– 4-to-26 MHz crystal oscillator

– Internal 16 MHz factory-trimmed RC

– 32 kHz oscillator for RTC with calibration

– Internal 32 kHz RC with calibration

• Power consumption

– Run: 128 µA/MHz (peripheral off)

– Stop (Flash in Stop mode, fast wakeup

time): 42 µA typ @ 25 °C;

65 µA max @25 °C

– Stop (Flash in Deep power down mode,

slow wakeup time): down to 10 µA typ@

25 °C; 28 µA max @25 °C

– Standby: 2.4 µA @25 °C / 1.7 V without

RTC; 12 µA @85 °C @1.7 V

–V

BAT

supply for RTC: 1 µA @25 °C

• 1×12-bit, 2.4 MSPS A/D converter: up to 16

channels

• General-purpose DMA: 16-stream DMA

controllers with FIFOs and burst support

• Up to 11 timers: up to six 16-bit, two 32-bit

timers up to 84 MHz, each with up to

4 IC/OC/PWM or pulse counter and quadrature

(incremental) encoder input, two watchdog

timers (independent and window) and a

SysTick timer

• Debug mode

– Serial wire debug (SWD) & JTAG

interfaces

–Cortex

-M4 Embedded Trace Macrocell™

• Up to 81 I/O ports with interrupt capability

– All IO ports 5 V tolerant

– Up to 78 fast I/Os up to 42 MHz

• Up to 11 communication interfaces

– Up to 3 × I

C interfaces (1Mbit/s,

SMBus/PMBus)

– Up to 3 USARTs (2 x 10.5 Mbit/s, 1 x

5.25 Mbit/s), ISO 7816 interface, LIN, IrDA,

modem control)

– Up to 4 SPIs (up to 42 Mbits/s at f

CPU

= 84

MHz), SPI2 and SPI3 with muxed full-

duplex I

S to achieve audio class accuracy

via internal audio PLL or external clock

– SDIO interface

• Advanced connectivity

– USB 2.0 full-speed device/host/OTG

controller with on-chip PHY

• CRC calculation unit

• 96-bit unique ID

• RTC: subsecond accuracy, hardware calendar

• All packages are ECOPACK2

Table 1. Device summary

Reference Part number

STM32F401xB

STM32F401CB, STM32F401RB,

STM32F401VB

STM32F401xC

STM32F401CC, STM32F401RC,

STM32F401VC

LQFP10

0 (14X14 mm)

LQFP64 (10×10 mm)

)%*$

UFQFPN48

(7×7 mm)

UFBGA100

(7x7 mm)

WLCSP49

(2.965x2.965 mm)

www.st.com

Downloaded from Arrow.com.

Summary of content (139 pages)

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STM32F401xB STM32F401xC Arm® Cortex®-M4 32-bit MCU+FPU, 105 DMIPS, 256KB Flash / 64KB RAM, 11 TIMs, 1 ADC, 11 comm. interfaces Datasheet - production data Features • Dynamic efficiency line with BAM (batch acquisition mode) – 1.7 V to 3.6 V power supply – -40 °C to 85/105/125 °C temperature range • Core: Arm® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 84 MHz, memory protection unit, 105 DMIPS/ 1.
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Contents STM32F401xB STM32F401xC Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1 Arm® Cortex®-M4 with FPU core with embedded Flash and SRAM . . . . 15 3.
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STM32F401xB STM32F401xC Contents 3.19.3 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.19.4 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.19.5 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.20 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.
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Contents 7 STM32F401xB STM32F401xC 6.3.6 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.3.7 Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.3.8 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.3.9 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.3.10 PLL characteristics . . . . . . . . . . . . . . . . . . .
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STM32F401xB STM32F401xC List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Device summary . . . . . . . . . . . . . . . . . . . .
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List of tables Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. 6/139 Downloaded from Arrow.com.
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STM32F401xB STM32F401xC List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42.
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List of figures Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. 8/139 Downloaded from Arrow.com. STM32F401xB STM32F401xC package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 WLCSP49 - 49-ball, 2.999 mm, 0.4 mm pitch wafer level chip scale recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . .
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STM32F401xB STM32F401xC 1 Introduction Introduction This datasheet provides the description of the STM32F401xB/STM32F401xC microcontrollers, based on an Arm® (a) core®. This document has to be read in conjunction with RM0368 reference manual, which is available from the STMicroelectronics website www.st.com. It includes all information concerning Flash memory programming. For information on the Cortex®-M4 core, refer to the Cortex®-M4 programming manual (PM0214) available from www.st.com. a.
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Description 2 STM32F401xB STM32F401xC Description The STM32F401XB/STM32F401XC devices are based on the high-performance Arm® Cortex® -M4 32-bit RISC core operating at a frequency of up to 84 MHz. The Cortex®-M4 core features a Floating point unit (FPU) single precision which supports all Arm single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security.
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STM32F401xB STM32F401xC Description Table 2.
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Description 2.1 STM32F401xB STM32F401xC Compatibility with STM32F4 Series The STM32F401xB/STM32F401xC are fully software and feature compatible with the STM32F4 series (STM32F42x, STM32F43x, STM32F41x, STM32F405 and STM32F407) The STM32F401xB/STM32F401xC can be used as drop-in replacement of the other STM32F4 products but some slight changes have to be done on the PCB board. Figure 1.
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STM32F401xB STM32F401xC Description Figure 2.
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Description STM32F401xB STM32F401xC Figure 3. STM32F401xB/STM32F401xC block diagram -7$* 6: 038 19,& (70 ' %86 '0$ 6WUHDPV ),)2 '0$ 6WUHDPV ),)2 )ODVK XS WR .% 65$0 .% $+% 0+] &)&/ 6 %86 $&&(/ &$&+( )38 0(9 $50 &RUWH[ 0 0+] , %86 $+% EXV PDWUL[ 6 0 1-7567 -7', -7&. 6:&/. -7'2 6:' -7'2 75$&(&/.
PAGE 15
STM32F401xB STM32F401xC Functional overview 3 Functional overview 3.1 Arm® Cortex®-M4 with FPU core with embedded Flash and SRAM The Arm® Cortex®-M4 with FPU processor is the latest generation of Arm processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts.
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Functional overview 3.4 STM32F401xB STM32F401xC Embedded Flash memory The devices embed up to 256 Kbytes of Flash memory available for storing programs and data. 3.5 CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity.
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STM32F401xB STM32F401xC 3.8 Functional overview DMA controller (DMA) The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each. They are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth (AHB/APB).
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Functional overview 3.11 STM32F401xB STM32F401xC Clocks and startup On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The 16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy at 25 °C. The application can then select as system clock either the RC oscillator or an external 4-26 MHz clock source. This clock can be monitored for failure.
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STM32F401xB STM32F401xC Functional overview 3.14 Power supply supervisor 3.14.1 Internal reset ON This feature is available for VDD operating voltage range 1.8 V to 3.6 V. The internal power supply supervisor is enabled by holding PDR_ON high. The devices have an integrated power-on reset (POR) / power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry. At power-on, POR is always active, and ensures proper operation starting from 1.8 V. After the 1.
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Functional overview STM32F401xB STM32F401xC The VDD specified threshold, below which the device must be maintained under reset, is 1.7 V (see Figure 6). A comprehensive set of power-saving mode allows to design low-power applications. When the internal reset is OFF, the following integrated features are no longer supported: • The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled. • The brownout reset (BOR) circuitry must be disabled.
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STM32F401xB STM32F401xC 3.15.1 Functional overview Regulator ON On packages embedding the BYPASS_REG pin, the regulator is enabled by holding BYPASS_REG low. On all other packages, the regulator is always enabled.
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Functional overview STM32F401xB STM32F401xC Figure 7. Regulator OFF 9 ([WHUQDO 9&$3B SRZHU $SSOLFDWLRQ UHVHW VXSSO\ VXSHUYLVRU ([W UHVHW FRQWUROOHU DFWLYH VLJQDO RSWLRQDO ZKHQ 9&$3B 0LQ 9 9'' 3$ 9'' 1567 %<3$66B5(* 9 9&$3B 9&$3B DL 9 The following conditions must be respected: Note: 22/139 Downloaded from Arrow.com. • VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection between power domains.
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STM32F401xB STM32F401xC Functional overview Figure 8. Startup in regulator OFF: slow VDD slope power-down reset risen after VCAP_1/VCAP_2 stabilization 9'' 3'5 9 9 0LQ 9 9&$3B 9&$3B WLPH 1567 WLPH 06Y 9 1. This figure is valid whatever the internal reset mode (ON or OFF). Figure 9. Startup in regulator OFF mode: fast VDD slope power-down reset risen before VCAP_1/VCAP_2 stabilization 9'' 3'5 9 9&$3B 9&$3B 9 0LQ 9 1567 WLPH 3$ DVVHUWHG H[WHUQDOO\ WLPH 06Y
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Functional overview 3.15.3 STM32F401xB STM32F401xC Regulator ON/OFF and internal power supply supervisor availability Table 3.
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STM32F401xB STM32F401xC 3.17 Functional overview Low-power modes The devices support three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: • Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. • Stop mode The Stop mode achieves the lowest power consumption while retaining the contents of SRAM and registers. All clocks in the 1.
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Functional overview STM32F401xB STM32F401xC Table 4.
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STM32F401xB STM32F401xC 3.19.2 Functional overview General-purpose timers (TIMx) There are seven synchronizable general-purpose timers embedded in the STM32F401xB/STM32F401xC (see Table 4 for differences). • TIM2, TIM3, TIM4, TIM5 The STM32F401xB/STM32F401xC devices are 4 full-featured general-purpose timers: TIM2, TIM5, TIM3, and TIM4.The TIM2 and TIM5 timers are based on a 32-bit autoreload up/downcounter and a 16-bit prescaler.
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Functional overview 3.20 STM32F401xB STM32F401xC Inter-integrated circuit interface (I2C) Up to three I2C bus interfaces can operate in multimaster and slave modes. They can support the standard (up to 100 kHz) and fast (up to 400 kHz) modes. The I2C bus frequency can be increased up to 1 MHz. For more details about the complete solution, please contact your local ST sales representative.They also support the 7/10-bit addressing mode and the 7-bit dual addressing mode (as slave).
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STM32F401xB STM32F401xC 3.22 Functional overview Serial peripheral interface (SPI) The devices feature up to four SPIs in slave and master modes in full-duplex and simplex communication modes. SPI1 and SPI4 can communicate at up to 42 Mbit/s, SPI2 and SPI3 can communicate at up to 21 Mbit/s. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes.
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Functional overview 3.26 STM32F401xB STM32F401xC Universal serial bus on-the-go full-speed (OTG_FS) The devices embed an USB OTG full-speed device/host/OTG peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and with the OTG 1.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator.
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STM32F401xB STM32F401xC Functional overview As the offset of the temperature sensor varies from chip to chip due to process variation, the internal temperature sensor is mainly suitable for applications that detect temperature changes instead of absolute temperatures. If an accurate temperature reading is needed, then an external temperature sensor part should be used. 3.
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Pinouts and pin description 4 STM32F401xB STM32F401xC Pinouts and pin description Figure 10.
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STM32F401xB STM32F401xC Pinouts and pin description 3% 3% 3% 3% 3$ 3$ 3% 3% %227 966 9%$7 3% 9'' Figure 11.
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Pinouts and pin description STM32F401xB STM32F401xC 9%$7 3& 3& 26& B,1 3% 3% %227 3% 3% 3% 3% 3% 3' 3& 3& 3& 3$ 3$ /4)3 9'' 966 3$ 3$ 3$ 3$ 3$ 3$ 3& 3& 3& 3& 3% 3% 3% 3% 3$ 966 9'' 3$ 3$ 3$ 3$ 3& 3& 3% 3% 3% 3% 9&$3B 966 9'' 3& 26& B287 3+ 26&B,
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STM32F401xB STM32F401xC Pinouts and pin description 6$$ 633 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! Figure 13.
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Pinouts and pin description STM32F401xB STM32F401xC Figure 14.
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STM32F401xB STM32F401xC Pinouts and pin description Table 7.
PAGE 38
Pinouts and pin description STM32F401xB STM32F401xC WLCSP49 LQFP64 LQFP100 UFBGA100 3 C7 3 8 D1 PC14OSC32_IN (PC14) I/O FT 4 C6 4 9 E1 PC15OSC32_OUT (PC15) I/O FT - - - 10 F2 VSS S - - - - - - - 11 G2 VDD S - - - - 5 D7 5 12 F1 PH0-OSC_IN (PH0) I/O FT (4) EVENTOUT OSC_IN 6 D6 6 13 G1 PH1OSC_OUT (PH1) I/O FT (4) EVENTOUT OSC_OUT 7 E7 7 14 H2 NRST I/O FT - EVENTOUT - - - 8 15 H1 PC0 I/O FT - EVENTOUT ADC1_IN10 - - 9 16 J2 P
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STM32F401xB STM32F401xC Pinouts and pin description WLCSP49 LQFP64 LQFP100 UFBGA100 Pin name (function after reset)(1) 13 E4 17 26 L3 PA3 - - 18 27 - VSS S - - - - - - 19 28 - VDD S - - - - - - - - E3 BYPASS_ REG I FT - - - I/O FT Notes UQFN48 Pin type Pin Number I/O structure Table 8.
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Pinouts and pin description STM32F401xB STM32F401xC WLCSP49 LQFP64 LQFP100 UFBGA100 Pin name (function after reset)(1) - - - 45 M11 PE14 I/O FT - SPI4_MOSI, TIM1_CH4, EVENTOUT - - - - 46 M12 PE15 I/O FT - TIM1_BKIN, EVENTOUT - 21 E3 29 47 L10 PB10 I/O FT - SPI2_SCK/I2S2_CK, I2C2_SCL, TIM2_CH3, EVENTOUT - - - - - K9 PB11 I/O FT - TIM2_CH4, I2C2_SDA, EVENTOUT - Notes UQFN48 Pin type Pin Number I/O structure Table 8.
PAGE 41
STM32F401xB STM32F401xC Pinouts and pin description WLCSP49 LQFP64 LQFP100 UFBGA100 Pin name (function after reset)(1) - - 39 65 E10 PC8 I/O FT - USART6_CK, TIM3_CH3, SDIO_D0, EVENTOUT - - - 40 66 D12 PC9 I/O FT - I2S_CKIN, I2C3_SDA, TIM3_CH4, SDIO_D1, MCO_2, EVENTOUT - 29 D1 41 67 D11 PA8 I/O FT - I2C3_SCL, USART1_CK, TIM1_CH1, OTG_FS_SOF, MCO_1, EVENTOUT - 30 D2 42 68 D10 PA9 I/O FT - I2C3_SMBA, USART1_TX, TIM1_CH2, EVENTOUT OTG_FS_VBUS 31 C2 43 69 C12 P
PAGE 42
Pinouts and pin description STM32F401xB STM32F401xC WLCSP49 LQFP64 LQFP100 UFBGA100 Pin name (function after reset)(1) - - - 82 B9 PD1 I/O FT - EVENTOUT - - - 54 83 C8 PD2 I/O FT - TIM3_ETR, SDIO_CMD, EVENTOUT - - - - 84 B8 PD3 I/O FT - SPI2_SCK/I2S2_CK, USART2_CTS, EVENTOUT - - - - 85 B7 PD4 I/O FT - USART2_RTS, EVENTOUT - - - - 86 A6 PD5 I/O FT - USART2_TX, EVENTOUT - - - - 87 B6 PD6 I/O FT - SPI3_MOSI/I2S3_SD, USART2_RX, EVENTOUT - - -
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STM32F401xB STM32F401xC Pinouts and pin description Table 8. STM32F401xB/STM32F401xC pin definitions (continued) UQFN48 WLCSP49 LQFP64 LQFP100 UFBGA100 Pin name (function after reset)(1) Pin type I/O structure Notes Pin Number Alternate functions 47 A6 63 99 - VSS S - - - - - B6 - - H3 PDR_ON I FT - - - 48 A7 - VDD S - - - - 64 100 Additional functions 1. Function availability depends on the chosen device. 2.
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Downloaded from Arrow.com. - - PH1 SYS_AF PH0 Port AF00 - - TIM1/TIM2 AF01 - - TIM3/ TIM4/ TIM5 AF02 - - TIM9/ TIM10/ TIM11 AF03 - - I2C1/I2C2/ I2C3 AF04 - - SPI1/SPI2/ I2S2/SPI3/ I2S3/SPI4 AF05 - - SPI2/I2S2/ SPI3/ I2S3 AF06 - - SPI3/I2S3/ USART1/ USART2 AF07 - - USART6 AF08 Table 9.
PAGE 50
Memory mapping 5 STM32F401xB STM32F401xC Memory mapping The memory map is shown in Figure 15. Figure 15. Memory map 5HVHUYHG [( [)))) )))) &RUWH[ 0 LQWHUQDO SHULSKHUDOV [( [( ) )))) ['))) )))) 5HVHUYHG [ [ )))) $+% 5HVHUYHG [)))) )))) [( ['))) )))) 0E\WH EORFN &RUWH[ 0 V LQWHUQDO SHULSKHUDOV [ [ [ ))) )))) [ )) $+% 0E\WH EORFN 1RW XVHG [& [%))) )))) [ 5HVHUYHG [ &
PAGE 51
STM32F401xB STM32F401xC Memory mapping Table 10.
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Memory mapping STM32F401xB STM32F401xC Table 10. STM32F401xB/STM32F401xC register boundary addresses (continued) Bus APB2 52/139 Downloaded from Arrow.com.
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STM32F401xB STM32F401xC Memory mapping Table 10.
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Electrical characteristics STM32F401xB STM32F401xC 6 Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range).
PAGE 55
STM32F401xB STM32F401xC 6.1.5 Electrical characteristics Pin input voltage The input voltage measurement on a pin of the device is described in Figure 17. Figure 17. Input voltage measurement -#5 PIN 6). -3 6 DS9716 Rev 11 55/139 113 Downloaded from Arrow.com.
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Electrical characteristics 6.1.6 STM32F401xB STM32F401xC Power supply scheme Figure 18. Power supply scheme 9%$7 9%$7 WR 9 *3,2V ,1 9&$3B 9&$3B 9'' 966 î Q) î ) /HYHO VKLIWHU 287 î ) RU î ) 9'' %DFNXS FLUFXLWU\ 26& . 57& :DNHXS ORJLF %DFNXS UHJLVWHUV 3RZHU VZLWFK ,2 /RJLF .HUQHO ORJLF &38 GLJLWDO 5$0 9ROWDJH UHJXODWRU )ODVK PHPRU\ %<3$66B5(* 3'5B21 9'' 9''$ 95() Q) ) 5HVHW FRQWUROOHU Q) ) 95()
PAGE 57
STM32F401xB STM32F401xC 6.1.7 Electrical characteristics Current consumption measurement Figure 19. Current consumption measurement scheme ,''B9%$7 9%$7 ,'' 9'' 9''$ DL 6.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 11: Voltage characteristics, Table 12: Current characteristics, and Table 13: Thermal characteristics may cause permanent damage to the device.
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Electrical characteristics STM32F401xB STM32F401xC Table 12. Current characteristics Symbol Ratings Max.
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STM32F401xB STM32F401xC Electrical characteristics 6.3 Operating conditions 6.3.1 General operating conditions Table 14. General operating conditions Symbol fHCLK Parameter Internal AHB clock frequency Conditions Min Typ Max Power Scale3: Regulator ON, VOS[1:0] bits in PWR_CR register = 0x01 0 - 60 Power Scale2: Regulator ON, VOS[1:0] bits in PWR_CR register = 0x10 0 - 84 fPCLK1 Internal APB1 clock frequency - 0 - 42 fPCLK2 Internal APB2 clock frequency - 0 - 84 - 1.
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Electrical characteristics STM32F401xB STM32F401xC Table 14.
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STM32F401xB STM32F401xC Electrical characteristics 1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no wait state is required. 2. Thanks to the ART accelerator and the 128-bit Flash memory, the number of wait states given here does not impact the execution speed from Flash memory since the ART accelerator allows to achieve a performance equivalent to 0 wait state program execution. 3. Refer to Table 56: I/O AC characteristics for frequencies vs.
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Electrical characteristics 6.3.4 STM32F401xB STM32F401xC Operating conditions at power-up / power-down (regulator OFF) Subject to general operating conditions for TA. Table 18. Operating conditions at power-up / power-down (regulator OFF)(1) Symbol tVDD tVCAP Parameter Conditions Min Max VDD rise time rate Power-up 20 ∞ VDD fall time rate Power-down 20 ∞ VCAP_1 and VCAP_2 rise time rate Power-up 20 ∞ VCAP_1 and VCAP_2 fall time rate Power-down 20 ∞ Unit µs/V 1.
PAGE 63
STM32F401xB STM32F401xC Electrical characteristics Table 19. Embedded reset and power control block characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit - - 40 - mV Falling edge 2.13 2.19 2.24 Rising edge 2.23 2.29 2.33 Brownout level 2 threshold Falling edge 2.44 2.50 2.56 Rising edge 2.53 2.59 2.63 Brownout level 3 threshold Falling edge 2.75 2.83 2.88 Rising edge 2.85 2.92 2.
PAGE 64
Electrical characteristics STM32F401xB STM32F401xC Typical and maximum current consumption The MCU is placed under the following conditions: • All I/O pins are in input mode with a static value at VDD or VSS (no load). • All peripherals are disabled except if it is explicitly mentioned. • The Flash memory access time is adjusted to both fHCLK frequency and VDD ranges (refer to Table 15: Features depending on the operating power supply range).
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STM32F401xB STM32F401xC Electrical characteristics Table 21. Typical and maximum current consumption, code with data processing (ART accelerator disabled) running from SRAM Max(1) Symbol Parameter Conditions External clock, all peripherals enabled(2)(3) IDD Supply current in Run mode External clock, all peripherals disabled(3) fHCLK (MHz) Typ 84 TA= 25 °C TA= 85 °C TA= 105 °C TA= 125 °C 20.2 21 22 23 24.1 60 14.7 15 16 18 19.1 40 10.7 11 12 13 14.1 20 5.7 6 7 8 9.
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Electrical characteristics STM32F401xB STM32F401xC Table 23. Typical and maximum current consumption in run mode, code with data processing (ART accelerator enabled except prefetch) running from Flash memory - VDD = 3.3 V Max(1) Symbol Parameter Conditions fHCLK (MHz) Typ 84 External clock, all peripherals enabled(2)(3) IDD Supply current in Run mode External clock, all peripherals disabled(3) TA = 25 °C TA = 85 °C 22.5 23 24 25 26.1 60 14.8 16 17 18 19.1 40 11.0 12 13 14 15.
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STM32F401xB STM32F401xC Electrical characteristics Table 25. Typical and maximum current consumption in run mode, code with data processing (ART accelerator enabled with prefetch) running from Flash memory Max(1) Symbol Parameter Conditions fHCLK (MHz) Typ 84 External clock, all peripherals enabled(2)(3) IDD Supply current in Run mode External clock, all peripherals disabled(3) TA = 25 °C TA = 85 °C 31.8 33 35 36 37.6 60 21.8 22 23 24 25.1 40 16.0 17 18 19 20.1 30 12.
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Electrical characteristics STM32F401xB STM32F401xC 4. Same current consumption for fHCLK at 30 MHz and 20 MHz due to VCO running slower at 30 MHz. Table 27. Typical and maximum current consumptions in Stop mode - VDD = 1.
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STM32F401xB STM32F401xC Electrical characteristics Table 30. Typical and maximum current consumption in Standby mode - VDD=3.3 V Symbol Parameter Supply current IDD_STBY in Standby mode Conditions Low-speed oscillator (LSE) and RTC ON RTC and LSE OFF Typ(1) Max(2) TA = 25 °C TA = TA = TA = TA = 25 °C 85 °C 105 °C 125 °C 2.8 2.1 5.0 (3) 4.0 14.0 28.0 13.0 27.0 58 Unit µA (3) 55 1. When the PDR is OFF (internal reset is OFF), the typical current consumption is reduced by 1.2 µA. 2.
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Electrical characteristics STM32F401xB STM32F401xC Figure 21. Typical VBAT current consumption (LSE and RTC ON) )$$?6"!4 ! 6 6 6 6 6 6 6 6 6 # # # # # 4EMPERATURE -3 6 I/O system current consumption The current consumption of the I/O system has two components: static and dynamic. I/O static current consumption All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low.
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STM32F401xB STM32F401xC Electrical characteristics pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin: I SW = V DD × f SW × C where ISW is the current sunk by a switching I/O to charge/discharge the capacitive load VDD is the MCU supply voltage fSW is the I/O switching frequency C is the total capacitance seen by the I/O pin: C = CINT+ CEXT The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency.
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Electrical characteristics STM32F401xB STM32F401xC Table 32. Switching output I/O current consumption Symbol Parameter Conditions(1) VDD = 3.3 V C = CINT(2) VDD = 3.3 V CEXT = 0 pF C = CINT + CEXT + CS IDDIO I/O switching current VDD = 3.3 V CEXT =10 pF C = CINT + CEXT + CS VDD = 3.3 V CEXT = 22 pF C = CINT + CEXT + CS VDD = 3.3 V CEXT = 33 pF C = CINT + CEXT + CS I/O toggling frequency (fSW) 2 MHz 0.05 8 MHz 0.15 25 MHz 0.45 50 MHz 0.85 60 MHz 1.00 84 MHz 1.40 2 MHz 0.10 8 MHz 0.
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STM32F401xB STM32F401xC Electrical characteristics On-chip peripheral current consumption The MCU is placed under the following conditions: • At startup, all I/O pins are in analog input configuration. • All peripherals are disabled unless otherwise mentioned. • The ART accelerator is ON. • Voltage Scale 2 mode selected, internal digital voltage V12 = 1.26 V. • HCLK is the system clock at 84 MHz. fPCLK1 = fHCLK/2, and fPCLK2 = fHCLK.
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Electrical characteristics STM32F401xB STM32F401xC Table 33. Peripheral current consumption (continued) Peripheral IDD (typ) TIM1 5.71 TIM9 2.86 TIM10 1.79 TIM11 2.02 (2) ADC1 2.98 SPI1 1.19 USART1 3.10 USART6 2.86 SDIO 5.95 SPI4 1.31 SYSCFG 0.71 APB2 (up to 84 MHz) Unit µA/MHz 1. I2SMOD bit set in SPI_I2SCFGR register, and then the I2SE bit set to enable I2S peripheral. 2. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.
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STM32F401xB STM32F401xC 6.3.8 Electrical characteristics External clock source characteristics High-speed external user clock generated from an external source In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O. The external clock signal has to respect the Table 54. However, the recommended clock input waveform is shown in Figure 22.
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Electrical characteristics STM32F401xB STM32F401xC Table 36. Low-speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit - 32.768 1000 kHz 0.7VDD - VDD VSS - 0.
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STM32F401xB STM32F401xC Electrical characteristics Figure 23. Low-speed external clock source AC timing diagram 9/6(+ 9/6(/ WU /6( WI /6( W W: /6( W: /6( 7/6( I/6(BH[W ([WHUQDO FORFN VRXUFH ,/ 26& B,1 670 ) DL High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 26 MHz crystal/ceramic resonator oscillator.
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Electrical characteristics STM32F401xB STM32F401xC can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com. Figure 24.
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STM32F401xB STM32F401xC Electrical characteristics Figure 25. Typical application with a 32.768 kHz crystal 5HVRQDWRU ZLWK LQWHJUDWHG FDSDFLWRUV &/ I/6( 26& B,1 %LDV 5) FRQWUROOHG JDLQ N+ ] UHVRQDWRU 26& B28 7 &/ 670 ) DL 6.3.9 Internal clock source characteristics The parameters given in Table 39 and Table 40 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 14. High-speed internal (HSI) RC oscillator Table 39.
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Electrical characteristics STM32F401xB STM32F401xC Figure 26. ACCHSI versus temperature $&&+6, 7$ & 0LQ 0D[ 7\SLFDO 06Y 9 1. Guaranteed by characterization. Low-speed internal (LSI) RC oscillator Table 40. LSI oscillator characteristics (1) Symbol fLSI(2) tsu(LSI) (3) IDD(LSI)(3) Parameter Min Typ Max Unit 17 32 47 kHz LSI oscillator startup time - 15 40 µs LSI oscillator power consumption - 0.4 0.6 µA Frequency 1.
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STM32F401xB STM32F401xC Electrical characteristics Figure 27. ACCLSI versus temperature MAX AVG MIN .ORMALIZED DEVIATI ON 4EMPERAT URE # -3 6 6.3.10 PLL characteristics The parameters given in Table 41 and Table 42 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 14. Table 41.
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Electrical characteristics STM32F401xB STM32F401xC 1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared between PLL and PLLI2S. 2. Guaranteed by design. 3. The use of two PLLs in parallel can degrade the Jitter up to +30%. 4. Guaranteed by characterization. Table 42. PLLI2S (audio PLL) characteristics Symbol Parameter Conditions Min Typ Max fPLLI2S_IN PLLI2S input clock(1) - 0.95(2) 1 2.
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STM32F401xB STM32F401xC 6.3.11 Electrical characteristics PLL spread spectrum clock generation (SSCG) characteristics The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic interferences (see Table 49: EMI characteristics for WLCSP49). It is available only on the main PLL. Table 43. SSCG parameters constraint Symbol Parameter Min Typ Max(1) Unit fMod Modulation frequency - - 10 KHz md Peak modulation depth 0.
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Electrical characteristics STM32F401xB STM32F401xC Figure 28 and Figure 29 show the main PLL output clock waveforms in center spread and down spread modes, where: F0 is fPLL_OUT nominal. Tmode is the modulation period. md is the modulation depth. Figure 28. PLL output clock waveforms in center spread mode &REQUENCY 0,,?/54 MD & MD TMODE 4IME XTMODE AI Figure 29. PLL output clock waveforms in down spread mode )UHTXHQF\ 3//B287 ) [PG WPRGH 7LPH [WPRGH DL E 6.3.
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STM32F401xB STM32F401xC Electrical characteristics Table 45.
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Electrical characteristics STM32F401xB STM32F401xC Table 46. Flash memory programming with VPP voltage (continued) Symbol Parameter Conditions Min(1) Typ Max(1) Unit VPP VPP voltage range - 7 - 9 V IPP Minimum current sunk on the VPP pin - 10 - - mA Cumulative time during which VPP is applied - - - 1 hour tVPP(3) 1. Guaranteed by design. 2. The maximum programming time is measured after 100K erase operations. 3. VPP should only be connected during programming/erasing.
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STM32F401xB STM32F401xC Electrical characteristics Table 48. EMS characteristics for LQFP100 package Symbol Parameter Conditions Level/ Class VFESD Voltage limits to be applied on any I/O pin to induce a functional disturbance VDD = 3.3 V, LQFP100, WLCSP49, TA = +25 °C, fHCLK = 84 MHz, conforms to IEC 61000-4-2 2B VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD = 3.
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Electrical characteristics STM32F401xB STM32F401xC Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application, executing EEMBC code, is running. This emission test is compliant with SAE IEC61967-2 standard which specifies the test board and the pin loading. Table 49. EMI characteristics for WLCSP49 Symbol Parameter Conditions Max vs. [fHSE/fCPU] Monitored frequency band Unit 25/84 MHz SEMI Peak level VDD = 3.
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STM32F401xB STM32F401xC Electrical characteristics Static latchup Two complementary static tests are required on six parts to assess the latchup performance: • A supply overvoltage is applied to each power supply pin • A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78A IC latchup standard. Table 52. Electrical sensitivities Symbol LU 6.3.
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Electrical characteristics STM32F401xB STM32F401xC Note: It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. 6.3.16 I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 54 are derived from tests performed under the conditions summarized in Table 14. All I/Os are CMOS and TTL compliant. Table 54.
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STM32F401xB STM32F401xC Electrical characteristics 2. Guaranteed by design. 3. With a minimum of 200 mV. 4. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins, Refer to Table 53: I/O current injection susceptibility 5. To sustain a voltage higher than VDD +0.3 V, the internal pull-up/pull-down resistors must be disabled. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins.
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Electrical characteristics STM32F401xB STM32F401xC In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 6.2. In particular: • The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating ΣIVDD (see Table 12).
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STM32F401xB STM32F401xC Electrical characteristics Table 56.
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Electrical characteristics STM32F401xB STM32F401xC 1. Guaranteed by characterization. 2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F4xx reference manual for a description of the GPIOx_SPEEDR GPIO port output speed register. 3. The maximum frequency is defined in Figure 31. 4. For maximum frequencies above 50 MHz and VDD > 2.4 V, the compensation cell should be used. Figure 31.
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STM32F401xB STM32F401xC Electrical characteristics Figure 32. Recommended NRST pin protection 9'' ([WHUQDO UHVHW FLUFXLW 1567 538 ,QWHUQDO 5HVHW )LOWHU ) 670 ) DL F 1. The reset network protects the device against parasitic resets. 2. The external capacitor must be placed as close as possible to the device. 3. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 57. Otherwise the reset is not taken into account by the device. 6.3.
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Electrical characteristics 6.3.19 STM32F401xB STM32F401xC Communications interfaces I2C interface characteristics The I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” opendrain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The I2C characteristics are described in Table59. Refer also to Section 6.3.
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STM32F401xB STM32F401xC Electrical characteristics Figure 33. I2C bus AC waveforms and measurement circuit 9''B, & 9''B, & 53 53 670 )[[ 56 6'$ ,ð& EXV 56 6&/ 67$57 5(3($7(' 67$57 67$57 WVX 67$ 6'$ WI 6'$ WU 6'$ WK 67$ WVX 6'$ WZ 672 67$ 6723 WK 6'$ WZ 6&/+ 6&/ WU 6&/ WZ 6&// WI 6&/ WVX 672 06Y 9 1. RS = series protection resistor. 2. RP = external pull-up resistor. 3. VDD_I2C is the I2C bus power supply. Table 60. SCL frequency (fPCLK1= 42 MHz, VDD = VDD_I2C = 3.
PAGE 98
Electrical characteristics STM32F401xB STM32F401xC SPI interface characteristics Unless otherwise specified, the parameters given in Table 61 for the SPI interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 14, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5VDD Refer to Section 6.3.
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STM32F401xB STM32F401xC Electrical characteristics Table 61. SPI dynamic characteristics(1) (continued) Symbol Parameter tv(MO) Data output valid time th(MO) Conditions Data output hold time Min Typ Max Unit Master mode (after enable edge) - 3 5 ns Master mode (after enable edge) 2 - - ns 1. Guaranteed by characterization. 2.
PAGE 100
Electrical characteristics STM32F401xB STM32F401xC Figure 36. SPI timing diagram - master mode(1) +LJK 166 LQSXW 6&. 2XWSXW &3+$ &32/ 6&. 2XWSXW WF 6&. &3+$ &32/ &3+$ &32/ &3+$ &32/ WVX 0, 0,62 ,13 87 WZ 6&.+ WZ 6&./ 06% ,1 WU 6&. WI 6&. %,7 ,1 /6% ,1 WK 0, 026, 287387 06% 287 WY 02 % , 7 287 /6% 287 WK 02 DL F 100/139 Downloaded from Arrow.com.
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STM32F401xB STM32F401xC Electrical characteristics I2S interface characteristics Unless otherwise specified, the parameters given in Table 62 for the I2S interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 14, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5VDD Refer to Section 6.3.
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Electrical characteristics STM32F401xB STM32F401xC Figure 37. I2S slave timing diagram (Philips protocol)(1) tc(CK) CK Input CPOL = 0 CPOL = 1 tw(CKH) th(WS) tw(CKL) WS input tv(SD_ST) tsu(WS) SDtransmit LSB transmit(2) MSB transmit Bitn transmit tsu(SD_SR) LSB transmit th(SD_SR) LSB receive(2) SDreceive th(SD_ST) MSB receive Bitn receive LSB receive ai14881b 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 38.
PAGE 103
STM32F401xB STM32F401xC Electrical characteristics USB OTG full speed (FS) characteristics This interface is present in USB OTG FS controller. Table 63. USB OTG FS startup time Symbol tSTARTUP(1) Parameter USB OTG FS transceiver startup time Max Unit 1 µs 1. Guaranteed by design. Table 64. USB OTG FS DC electrical characteristics Symbol Conditions USB OTG FS operating voltage Min.(1) Typ. Max.(1) Unit - 3.0(2) - 3.6 VDI(3) Differential input sensitivity I(USB_FS_DP/DM) 0.
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Electrical characteristics STM32F401xB STM32F401xC Figure 39. USB OTG FS timings: definition of data signal rise and fall time &URVV RYHU SRLQWV 'LIIHUHQWLDO GDWD OLQHV 9&56 966 WI WU DL E Table 65. USB OTG FS electrical characteristics(1) Driver characteristics Symbol Parameter Rise time(2) tr Fall tf trfm time(2) Conditions Min Max Unit CL = 50 pF 4 20 ns CL = 50 pF 4 20 ns tr/tf 90 110 % - 1.3 2.0 V Rise/ fall time matching VCRS Output signal crossover voltage 1.
PAGE 105
STM32F401xB STM32F401xC Electrical characteristics Table 66. ADC characteristics (continued) Symbol CADC(2) Parameter Conditions Internal sample and hold capacitor Min Typ Max Unit - 4 7 pF tlat(2) Injection trigger conversion latency fADC = 30 MHz - - 0.100 µs - - - 3(5) 1/fADC tlatr(2) Regular trigger conversion latency fADC = 30 MHz - - 0.
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Electrical characteristics STM32F401xB STM32F401xC Equation 1: RAIN max formula R AIN ( k – 0.5 ) - – R ADC = --------------------------------------------------------------N+2 f ADC × C ADC × ln ( 2 ) The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of sampling periods defined in the ADC_SMPR1 register. Table 67.
PAGE 107
STM32F401xB STM32F401xC Electrical characteristics Table 70. ADC dynamic accuracy at fADC = 18 MHz - limited test conditions(1) Symbol Parameter Test conditions ENOB Effective number of bits SINAD Signal-to-noise and distortion ratio SNR Signal-to-noise ratio THD Total harmonic distortion fADC =18 MHz VDDA = VREF+= 1.7 V Input Frequency = 20 KHz Temperature = 25 °C Min Typ Max Unit 10.3 10.4 - bits 64 64.2 - 64 65 - -67 -72 - dB 1. Guaranteed by characterization. Table 71.
PAGE 108
Electrical characteristics STM32F401xB STM32F401xC Figure 40. ADC accuracy characteristics ; ,3" )$%!, 6 2%& OR 6 $$! DEPENDING ON PACKAGE = %' %4 %/ %, %$ , 3")$%!, 6 33! 6$$! AI C 1. See also Table 68. 2. Example of an actual transfer curve. 3. Ideal transfer curve. 4. End point correlation line. 5.
PAGE 109
STM32F401xB STM32F401xC Electrical characteristics General PCB design guidelines Power supply decoupling should be performed as shown in Figure 42 or Figure 43, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 42. Power supply and reference decoupling (VREF+ not connected to VDDA) 670 ) 95() ) Q) 9''$ ) Q) 966$ 95() DL E 1.
PAGE 110
Electrical characteristics STM32F401xB STM32F401xC Figure 43. Power supply and reference decoupling (VREF+ connected to VDDA) 670 ) 95() 9''$ ) Q) 95() 966$ DL F 1. VREF+ and VREF- inputs are both available on UFBGA100. VREF+ is also available on LQFP100. When VREF+ and VREF- are not available, they are internally connected to VDDA and VSSA. 6.3.21 Temperature sensor characteristics Table 72.
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STM32F401xB STM32F401xC 6.3.22 Electrical characteristics VBAT monitoring characteristics Table 74. VBAT monitoring characteristics Symbol Parameter Min Typ Max Unit R Resistor bridge for VBAT - 50 - KΩ Q Ratio on VBAT measurement - 4 - - Error on Q –1 - +1 % ADC sampling time when reading the VBAT 1 mV accuracy 5 - - µs Er (1) TS_vbat(2)(2) 1. Guaranteed by design. 2. Shortest sampling time can be determined in the application by multiple iterations. 6.3.
PAGE 112
Electrical characteristics STM32F401xB STM32F401xC Refer to Section 6.3.16: I/O port characteristics for more details on the input/output characteristics. Figure 44. SDIO high-speed mode tf tr tC tW(CKH) tW(CKL) CK tOV tOH D, CMD (output) tISU tIH D, CMD (input) ai14887 Figure 45. SD default mode CK tOVD tOHD D, CMD (output) ai14888 Table 77.
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STM32F401xB STM32F401xC Electrical characteristics Table 77. Dynamic characteristics: SD / MMC characteristics(1)(2) (continued) Symbol Parameter Conditions Min Typ Max Unit CMD, D inputs (referenced to CK) in SD default mode tISUD Input setup time SD fpp = 24MHz 1.5 - - tIHD Input hold time SD fpp = 24MHz 0.5 - - ns CMD, D outputs (referenced to CK) in SD default mode tOVD Output valid default time SD fpp =24MHz - 4.5 6.5 tOHD Output hold default time SD fpp =24MHz 3.
PAGE 114
Package information 7 STM32F401xB STM32F401xC Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 7.1 WLCSP49 package information Figure 46. WLCSP49 - 49-ball, 2.965 x 2.965 mm, 0.
PAGE 115
STM32F401xB STM32F401xC Package information Table 79. WLCSP49 - 49-ball, 2.965 x 2.965 mm, 0.4 mm pitch wafer level chip scale package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.525 0.555 0.585 0.0207 0.0219 0.0230 A1 - 0.175 - - 0.0069 - A2 - 0.380 - - 0.0150 - A3 (2) - 0.025 - - 0.0010 - (3) 0.220 0.250 0.280 0.0087 0.0098 0.0110 D 2.930 2.965 3.000 0.1154 0.1167 0.1181 E 2.930 2.965 3.000 0.1154 0.1167 0.
PAGE 116
Package information STM32F401xB STM32F401xC Table 80. WLCSP49 recommended PCB design rules (0.4 mm pitch) Dimension Recommended values Pitch 0.4 mm Dpad 260 µm max. (circular) 220 µm recommended Dsm 300 µm min. (for 260 µm diameter pad) PCB pad design Non-solder mask defined via underbump allowed Device marking for WLCSP49 The following figure gives an example of topside marking orientation versus ball A1 identifier location. The printed markings may differ depending on the supply chain.
PAGE 117
STM32F401xB STM32F401xC 7.2 Package information UFQFPN48 package information Figure 49. UFQFPN48 - 48-lead, 7 x 7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package outline 3LQ LGHQWLILHU ODVHU PDUNLQJ DUHD ' $ ( ( 7 GGG 6HDWLQJ SODQH $ E H 'HWDLO < ' ([SRVHG SDG DUHD < ' / & [ SLQ FRUQHU 5 W\S 'HWDLO = ( = $ % B0(B9 1. Drawing is not to scale. 2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life. 3.
PAGE 118
Package information STM32F401xB STM32F401xC Table 81. UFQFPN48 - 48-lead, 7 x 7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package mechanical data (continued) inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. E2 5.500 5.600 5.700 0.2165 0.2205 0.2244 L 0.300 0.400 0.500 0.0118 0.0157 0.0197 T - 0.152 - - 0.0060 - b 0.200 0.250 0.300 0.0079 0.0098 0.0118 e - 0.500 - - 0.0197 - ddd - - 0.080 - - 0.0031 1.
PAGE 119
STM32F401xB STM32F401xC Package information Device marking for UFQFPN48 The following figure gives an example of topside marking orientation versus pin 1 identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 51.
PAGE 120
Package information 7.3 STM32F401xB STM32F401xC LQFP64 package information Figure 52. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline PP *$8*( 3/$1( F $ $ $ 6($7,1* 3/$1( & $ FFF & ' ' ' . / / 3,1 ,'(17,),&$7,21 ( ( ( E H :B0(B9 1. Drawing is not to scale. Table 82. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol 120/139 Downloaded from Arrow.com.
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STM32F401xB STM32F401xC Package information Table 82. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max E3 - 7.500 - - 0.2953 - e - 0.500 - - 0.0197 - K 0° 3.5° 7° 0° 3.5° 7° L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 53.
PAGE 122
Package information STM32F401xB STM32F401xC Device marking for LQFP64 The following figures give examples of topside marking orientation versus pin 1 identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 54. LQFP64 marking example (package top view) 5HYLVLRQ FRGH 3URGXFW LGHQWLILFDWLRQ 5 670 ) 5%7 'DWH FRGH < :: 3LQ LQGHQWLILHU 06Y 9 1.
PAGE 123
STM32F401xB STM32F401xC Package information Figure 55. LQFP64 marking example (package top view) 5HYLVLRQ FRGH 5 3URGXFW LGHQWLILFDWLRQ 670 ) 5%7 'DWH FRGH < :: 3LQ LGHQWLILHU 06Y 9 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use.
PAGE 124
Package information 7.4 STM32F401xB STM32F401xC LQFP100 package information Figure 56. LQFP100 - 100-pin, 14 x 14 mm, 100-pin low-profile quad flat package outline MM C ! ! ! 3%!4).' 0,!.% # '!5'% 0,!.% $ , $ ! + CCC # , $ 0). )$%.4)&)#!4)/. E 1. Drawing is not to scale. 124/139 Downloaded from Arrow.com.
PAGE 125
STM32F401xB STM32F401xC Package information Table 83. LQPF100 - 100-pin, 14 x 14 mm, 100-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. A - - 1.60 - - 0.063 A1 0.050 - 0.150 0.002 - 0.0059 A2 1.350 1.40 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 15.800 16.000 16.200 0.622 0.6299 0.6378 D1 13.800 14.000 14.200 0.5433 0.5512 0.
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Package information STM32F401xB STM32F401xC Figure 57. LQFP100 - 100-pin, 14 x 14 mm, 100-pin low-profile quad flat recommended footprint AI C 1. Dimensions are in millimeters. 126/139 Downloaded from Arrow.com.
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STM32F401xB STM32F401xC Package information Device marking for LQFP100 The following figure gives an example of topside marking orientation versus pin 1 identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 58.
PAGE 128
Package information 7.5 STM32F401xB STM32F401xC UFBGA100 package information Figure 59. UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package outline = 6HDWLQJ SODQH GGG = $ $ $ $ $ ( $ EDOO $ EDOO LGHQWLILHU LQGH[ DUHD = H ; ( $ = ' ' H < 0 %27720 9,(: E EDOOV HHH 0 = < ; III 0 = 723 9,(: $ & B0(B9 1. Drawing is not to scale. Table 84. UFBGA100 - 100-ball, 7 x 7 mm, 0.
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STM32F401xB STM32F401xC Package information Table 84. UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. ddd - - 0.080 - - 0.0031 eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 60. UFBGA100 - 100-ball, 7 x 7 mm, 0.
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Package information STM32F401xB STM32F401xC Device marking for UFBGA100 The following figure gives an example of topside marking orientation versus ball A1 identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 61.
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STM32F401xB STM32F401xC 7.6 Package information Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 14: General operating conditions on page 59. The maximum chip-junction temperature, TJ max.
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Ordering information 8 STM32F401xB STM32F401xC Ordering information Example: STM32 Device family STM32 = Arm®-based 32-bit microcontroller Product type F = General-purpose Device subfamily 401: 401 family Pin count C = 48/49 pins R = 64 pins V = 100 pins Flash memory size B = 128 Kbytes of Flash memory C = 256 Kbytes of Flash memory Package H = UFBGA T = LQFP U = UFQFPN Y = WLCSP Temperature range 6 = Industrial temperature range, - 40 to 85 °C 7 = Industrial temperature range, - 40 to 105 °C 3 = Indus
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STM32F401xB STM32F401xC 9 Revision history Revision history Table 87. Document revision history Date Revision Changes 23-Jul-2013 1 Initial release. 06-Sep-2013 2 Updated product status to production data Added I2C 1 MBit/s in Features Updated Figure 1: Compatible board design for LQFP100 package Added notes and revised the main function after reset columnn Table 8: STM32F401xB/STM32F401xC pin definitions.
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Revision history STM32F401xB STM32F401xC Table 87. Document revision history (continued) Date 16-May-2014 134/139 Downloaded from Arrow.com. Revision Changes 4 Change VDD/VDDA minimum value to 1.7 V. Changed number of EXTI lines in Section 3.10: External interrupt/event controller (EXTI). Updated Figure 18: Power supply scheme. Updated Table 11: Voltage characteristics, Table 12: Current characteristics andTable 14: General operating conditions. Added note 4.
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STM32F401xB STM32F401xC Revision history Table 87. Document revision history (continued) Date 06-Aug-2015 Revision Changes 5 Changed current consumption to 128 µA/MHz on cover page. Updated Table 3: Regulator ON/OFF and internal power supply supervisor availability for UFQFPN48. Updated Figure 10: STM32F401xB/STM32F401xC WLCSP49 pinout to show top view instead of bump view.
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Revision history STM32F401xB STM32F401xC Table 87. Document revision history (continued) Date 07-Sep-2016 136/139 Downloaded from Arrow.com. Revision Changes 6 Features: added dynamic efficiency, OTP memory and ECOPACK®2 compliance, updated clock/reset and supply management features. Updated signal corresponding to pin 21 in Figure 13: STM32F401xB/STM32F401xC LQFP100 pinout. Updated PB11 alternate functions in Table 8: STM32F401xB/STM32F401xC pin definitions and Table 9: Alternate function mapping.
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STM32F401xB STM32F401xC Revision history Table 87. Document revision history (continued) Date 28-Apr-2017 Revision Changes 7 Updated: – Features – Section 2: Description – Table 2: STM32F401xB/C features and peripheral counts – Table 13: Thermal characteristics – Table 14: General operating conditions – Table 19: Embedded reset and power control block characteristics – Table 20: Typical and maximum current consumption, code with data processing (ART accelerator disabled) running from SRAM - VDD = 1.
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Revision history STM32F401xB STM32F401xC Table 87. Document revision history (continued) Date Revision Changes 09-May-2017 8 Updated: – Note 1. in Figure 48: WLCSP49 marking example (package top view) – Note 1. in Figure 51: UFQFPN48 marking example (package top view) – Note 1. in Figure 54: LQFP64 marking example (package top view) – Note 1. in Figure 58: LQPF100 marking example (package top view) – Note 1.
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