Datasheet

DS9716 Rev 11 7/139
STM32F401xB STM32F401xC List of figures
8
List of figures
Figure 1. Compatible board design for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 2. Compatible board design for LQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 3. STM32F401xB/STM32F401xC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 4. Multi-AHB matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 5. Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 19
Figure 6. PDR_ON control with internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 7. Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 8. Startup in regulator OFF: slow V
DD
slope -
power-down reset risen after V
CAP_1
/V
CAP_2
stabilization. . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 9. Startup in regulator OFF mode: fast V
DD
slope -
power-down reset risen before V
CAP_1
/V
CAP_2
stabilization . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 10. STM32F401xB/STM32F401xC WLCSP49 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 11. STM32F401xB/STM32F401xC UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 12. STM32F401xB/STM32F401xC LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 13. STM32F401xB/STM32F401xC LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 14. STM32F401xB/STM32F401xC UFBGA100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 15. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 16. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 17. Input voltage measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 18. Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 19. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 20. External capacitor C
EXT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 21. Typical V
BAT
current consumption (LSE and RTC ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 22. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 23. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 24. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 25. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 26. ACC
HSI
versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 27. ACC
LSI
versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 28. PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 29. PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 30. FT I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 31. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 32. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 33. I
2
C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 34. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 35. SPI timing diagram - slave mode and CPHA = 1
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 36. SPI timing diagram - master mode
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 37. I
2
S slave timing diagram (Philips protocol)
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 38. I
2
S master timing diagram (Philips protocol)
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 39. USB OTG FS timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . 104
Figure 40. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 41. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 42. Power supply and reference decoupling (V
REF+
not connected to V
DDA
). . . . . . . . . . . . . 109
Figure 43. Power supply and reference decoupling (V
REF+
connected to V
DDA
). . . . . . . . . . . . . . . . 110
Figure 44. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 45. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 46. WLCSP49 - 49-ball, 2.965 x 2.965 mm, 0.4 mm pitch wafer level chip scale
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