Datasheet

DocID022691 Rev 7 85/137
STM32F373xx Electrical characteristics
114
Note: I/O pins are powered from V
DD
voltage except pins which can be used as SDADC inputs:
- The PB2, PB10 and PE7 to PE15 I/O pins are powered from V
DDSD12
.
- PB14 to PB15 and PD8 to PD15 I/O pins are powered from V
DDSD3
. All I/O pin ground is
internally connected to V
SS
.
V
DD
mentioned in the Table 52 represents power voltage for a given I/O pin (V
DD
or
V
DDSD12
or V
DDSD3
).
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 17 for standard I/Os, and in Figure 18 for
5 V tolerant I/Os. The following curves are design simulation results, not tested in
production.
Figure 17. TC and TTa I/O input characteristics - CMOS port
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