Datasheet

ManualsBrandsST ManualsEmbedded Processors & ControllersMicrocontroller 32bit 256KB LQFP

This is information on a product in full production.

June 2016 DocID022691 Rev 7 1/137

STM32F373xx

ARM

Cortex

-M4 32b MCU+FPU, up to 256KB Flash+32KB SRAM,

timers, 4 ADCs (16-bit Sig. Delta / 12-bit SAR), 3 DACs, 2 comp., 2.0-3.6 V

Datasheet - production data

Features

• Core: ARM

32-bit Cortex

-M4 CPU (72 MHz

max), single-cycle multiplication and HW

division, DSP instruction with FPU (floating-

point unit) and MPU (memory protection unit)

• 1.25 DMIPS/MHz (Dhrystone 2.1)

• Memories

– 64 to 256 Kbytes of Flash memory

– 32 Kbytes of SRAM with HW parity check

• CRC calculation unit

• Reset and power management

– Voltage range: 2.0 to 3.6 V

– Power-on/Power down reset (POR/PDR)

– Programmable voltage detector (PVD)

– Low power modes: Sleep, Stop, Standby

–V

BAT

supply for RTC and backup registers

• Clock management

– 4 to 32 MHz crystal oscillator

– 32 kHz oscillator for RTC with calibration

– Internal 8 MHz RC with x16 PLL option

– Internal 40 kHz oscillator

• Up to 84 fast I/Os

– All mappable on external interrupt vectors

– Up to 45 I/Os with 5 V tolerant capability

• 12-channel DMA controller

• One 12-bit, 1.0 µs ADC (up to 16 channels)

– Conversion range: 0 to 3.6 V

– Separate analog supply from 2.4 up to 3.6

• Three 16-bit Sigma Delta ADC

– Separate analog supply from 2.2 to 3.6 V,

up to 21 single/ 11 diff channels

• Three 12-bit DAC channels

• Two fast rail-to-rail analog comparators with

programmable input and output

• Up to 24 capacitive sensing channels

• 17 timers

– Two 32-bit timers and three 16-bit timers

with up to 4 IC/OC/PWM or pulse counters

– Two 16-bit timers with up to 2 IC/OC/PWM

or pulse counters

– Four 16-bit timers with up to 1 IC/OC/PWM

or pulse counter

– Independent and system watchdog timers

– SysTick timer: 24-bit down counter

– Three 16-bit basic timers to drive the DAC

• Calendar RTC with Alarm and periodic wakeup

from Stop/Standby

• Communication interfaces

– CAN interface (2.0B Active)

–Two I

Cs supporting Fast Mode Plus

(1 Mbit/s) with 20 mA current sink,

SMBus/PMBus, wakeup from STOP

– Three USARTs supporting synchronous

mode, modem control, ISO/IEC 7816, LIN,

IrDA, auto baud rate, wakeup feature

– Three SPIs (18 Mbit/s) with 4 to 16

programmable bit frames, muxed I2S

– HDMI-CEC bus interface

– USB 2.0 full speed interface

• Serial wire devices, JTAG, Cortex

-M4 ETM

• 96-bit unique ID

Table 1. Device summary

Reference Part numbers

STM32F373xx

STM32F373C8, STM32F373R8,

STM32F373V8, STM32F373CB,

STM32F373RB, STM32F373VB,

STM32F373CC, STM32F373RC,

STM32F373VC

LQFP64 (10 × 10 mm)

LQFP100 (14 × 14 mm)

LQFP48 (7 × 7 mm)

)%*$

UFBGA100 (7 x 7 mm)

www.st.com

Downloaded from Arrow.com.

Summary of content (137 pages)

PAGE 1
STM32F373xx ARM®Cortex®-M4 32b MCU+FPU, up to 256KB Flash+32KB SRAM, timers, 4 ADCs (16-bit Sig. Delta / 12-bit SAR), 3 DACs, 2 comp., 2.0-3.6 V Datasheet - production data Features )%*$ ® ® • Core: ARM 32-bit Cortex -M4 CPU (72 MHz max), single-cycle multiplication and HW division, DSP instruction with FPU (floatingpoint unit) and MPU (memory protection unit) • 1.25 DMIPS/MHz (Dhrystone 2.
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Contents STM32F373xx Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 ARM® Cortex®-M4 core with embedded Flash and SRAM . . . . . . . . . . . 13 3.2 Memory protection unit . . . . . . . . . . . . . . . . . .
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STM32F373xx Contents 3.17.2 Basic timers (TIM6, TIM7, TIM18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.17.3 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.17.4 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.17.5 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.18 Real-time clock (RTC) and backup registers . . . . . . . . . . . .
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Contents 7 STM32F373xx 6.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.3.10 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.3.11 EMC characteristics . . . . . . . . . . . . . . . . .
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STM32F373xx List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47.
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List of tables Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. 6/137 Downloaded from Arrow.com. STM32F373xx ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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STM32F373xx List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43.
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List of figures Figure 44. 8/137 Downloaded from Arrow.com. STM32F373xx LQFP64 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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STM32F373xx 1 Introduction Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32F373xx microcontrollers. This STM32F373xx datasheet should be read in conjunction with the RM0313 reference manual. The reference manual is available from the STMicroelectronics website www.st.com. For information on the Cortex®-M4 with FPU core, please refer to: • Cortex®-M4 with FPU Technical Reference Manual, available from www.arm.com.
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Description 2 STM32F373xx Description The STM32F373xx family is based on the high-performance ARM® Cortex®-M4 32-bit RISC core operating at a frequency of up to 72 MHz, and embedding a floating point unit (FPU), a memory protection unit (MPU) and an Embedded Trace Macrocell™ (ETM). The family incorporates high-speed embedded memories (up to 256 Kbyte of Flash memory, up to 32 Kbytes of SRAM), and an extensive range of enhanced I/Os and peripherals connected to two APB buses.
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STM32F373xx Description Table 2. Device overview STM32F 373Cx Peripheral STM32F 373Rx STM32F 373Vx Flash (Kbytes) 64 128 256 64 128 256 64 128 256 SRAM (Kbytes) 16 24 32 16 24 32 16 24 32 Timers General purpose 9 (16-bit) 2 (32 bit) Basic 3 (16-bit) SPI/I2S 3 2 Comm.
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Description STM32F373xx Figure 1. Block diagram )BUS #/24%8 - #05 $BUS FPD[ -(Z .6)# 3YSTEM .6)# "US-ATRIX *4234 *4$) *4#+ 37#,+ *4-3 37$!4 *4$/ AS !& 4RACE #ONTROLLER 0BUS &LASH OBL )NTERFACE *4!' 37 6'' &LASH UP TO +" 0/2 3500,9 2ESET 350%26)3)/. )NT 0/2 0$2 32!UP TO +" #9''$ 2# ,3 CHANNELS '0)/ 0/24 ! 0"; = '0)/ 0/24 " 0#; = '0)/ 0/24 # 0$; = '0)/ 0/24 $ 0&; BITS= 88 !& '0)/ 0/24 % 4)- &HANNEOV (75 DV $) 7,0 3$!$# ).
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STM32F373xx Functional overview 3 Functional overview 3.1 ARM® Cortex®-M4 core with embedded Flash and SRAM The ARM Cortex-M4 processor is the latest generation of ARM processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts.
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Functional overview 3.3 STM32F373xx Embedded Flash memory All STM32F373xx devices feature up to 256 Kbytes of embedded Flash memory available for storing programs and data. The Flash memory access time is adjusted to the CPU clock frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states above). 3.
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STM32F373xx Functional overview 3.7 Power management 3.7.1 Power supply schemes 3.7.2 • VDD: external power supply for I/Os and the internal regulator. It is provided externally through VDD pins, and can be 2.0 to 3.6 V. • VDDA = 2.0 to 3.6 V: – external analog power supplies for Reset blocks, RCs and PLL – supply voltage for 12-bit ADC, DACs and comparators (minimum voltage to be applied to VDDA is 2.4 V when the 12-bit ADC and DAC are used). • VDDSD12 and VDDSD3 = 2.2 to 3.
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Functional overview 3.7.4 STM32F373xx Low-power modes The STM32F373xx supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: • Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. • Stop mode Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the 1.
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STM32F373xx Functional overview Do not reconfigure GPIO pins which are not present on 48 and 64 pin packages to the analog mode. Additional current consumption in the range of tens of µA per pin can be observed if VDDA is higher than VDDIO. 3.10 Direct memory access (DMA) The flexible 12-channel, general-purpose DMA is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers.
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Functional overview 3.12 STM32F373xx 12-bit analog-to-digital converter (ADC) The 12-bit analog-to-digital converter is based on a successive approximation register (SAR) architecture. It has up to 16 external channels (AIN15:0) and 3 internal channels (temperature sensor, voltage reference, VBAT voltage measurement) performing conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs. The ADC can be served by the DMA controller.
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STM32F373xx 3.13 Functional overview 16-bit sigma delta analog-to-digital converters (SDADC) Three 16-bit sigma-delta analog-to-digital converters are embedded in the STM32F373xx. They have up to two separate supply voltages allowing the analog function voltage range to be independent from the STM32F373xx power supply. They share up to 21 input pins which may be configured in any combination of single-ended (up to 21) or differential inputs (up to 11). The conversion speed is up to 16.
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Functional overview 3.15 STM32F373xx Fast comparators (COMP) The STM32F373xx embeds 2 comparators with rail-to-rail inputs and high-speed output. The reference voltage can be internal or external (delivered by an I/O). The threshold can be one of the following: • DACs channel outputs • External I/O • Internal reference voltage (VREFINT) or submultiple (1/4 VREFINT, 1/2 VREFINT and 3/4 VREFINT) The comparators can be combined into a window comparator.
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STM32F373xx Functional overview Table 3. Capacitive sensing GPIOs available on STM32F373xx devices (continued) Group 3 4 Capacitive sensing signal name Pin name Capacitive sensing signal name Pin name TSC_G3_IO1 PC4 TSC_G7_IO1 PE2 TSC_G3_IO2 PC5 TSC_G7_IO2 PE3 TSC_G3_IO3 PB0 TSC_G7_IO3 PE4 TSC_G3_IO4 PB1 TSC_G7_IO4 PE5 TSC_G4_IO1 PA9 TSC_G8_IO1 PD12 TSC_G4_IO2 PA10 TSC_G8_IO2 PD13 TSC_G4_IO3 PA13 TSC_G8_IO3 PD14 TSC_G4_IO4 PA14 TSC_G8_IO4 PD15 Group 7 8 1.
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Functional overview 3.17 STM32F373xx Timers and watchdogs The STM32F373xx includes two 32-bit and nine 16-bit general-purpose timers, three basic timers, two watchdog timers and a SysTick timer. The table below compares the features of the advanced control, general purpose and basic timers. Table 5.
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STM32F373xx 3.17.1 Functional overview General-purpose timers (TIM2 to TIM5, TIM12 to TIM17, TIM19) There are eleven synchronizable general-purpose timers embedded in the STM32F373xx (see Table 5 for differences). Each general-purpose timer can be used to generate PWM outputs, or act as a simple time base.
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Functional overview 3.17.3 STM32F373xx Independent watchdog (IWDG) The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes.
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STM32F373xx • Functional overview Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision. The RTC clock sources can be: 3.19 • A 32.768 kHz external crystal • A resonator or oscillator • The internal low-power RC oscillator (typical frequency of 40 kHz) • The high-speed external clock divided by 32 Inter-integrated circuit interface (I2C) Two I2C bus interfaces can operate in multimaster and slave modes.
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Functional overview STM32F373xx Table 7. STM32F373xx I2C implementation (continued) I2C features(1) I2C1 I2C2 SMBus X X Wakeup from STOP X X 1. X = supported. 3.20 Universal synchronous/asynchronous receiver transmitter (USART) The STM32F373xx embeds three universal synchronous/asynchronous receiver transmitters (USART1, USART2 and USART3). All USARTs interfaces are able to communicate at speeds of up to 9 Mbit/s.
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STM32F373xx 3.21 Functional overview Serial peripheral interface (SPI)/Inter-integrated sound interfaces (I2S) Three SPIs are able to communicate at up to 18 Mbits/s in slave and master modes in fullduplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. The SPIs can be served by the DMA controller.
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Functional overview 3.24 STM32F373xx Universal serial bus (USB) The STM32F373xx embeds an USB device peripheral compatible with the USB full-speed 12 Mbs. The USB interface implements a full-speed (12 Mbit/s) function interface. It has software-configurable endpoint setting and suspend/resume support. The dedicated 48 MHz clock is generated from the internal main PLL (the clock source must use a HSE crystal oscillator). 3.
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STM32F373xx 4 Pinouts and pin description Pinouts and pin description 3$ 3$ 3% 3% 3% 3% 3% %227 3% 3% 966B 9''B Figure 2.
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Pinouts and pin description STM32F373xx 9''B 966B 3% 3% %227 3% 3% 3% 3% 3% 3' 3& 3& 3& 3$ 3$ Figure 3.
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STM32F373xx Pinouts and pin description 6$$? 633? 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! Figure 4.
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Pinouts and pin description STM32F373xx Figure 5. STM32F373xx UFBGA100 ballout ! 0% 0% 0" "//4 0$ 0$ 0" 0" 0! 0! 0! 0! " 0% 0% 0" 0" 0" 0$ 0$ 0$ 0$ 0# 0# 0! # 0# 0% 0% 0$ 0$ 0# 0& 0! $ 0# 0% 633? 0! 0! 0# 0# 6"!4 0# 0# 0# & 0& 0& 633? 6333$ ' 0& 0& 6$$? 6$$3$ ( 0# .
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STM32F373xx Pinouts and pin description Table 10. Legend/abbreviations used in the pinout table Name Pin name Abbreviation Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name Pin type I/O structure Notes Definition S Supply pin I Input only pin I/O Input / output pin FT 5 V tolerant I/O FTf 5 V tolerant I/O, FM+ capable TTa 3.3 V tolerant I/O directly connected to ADC TC Standard 3.
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Pinouts and pin description STM32F373xx Table 11.
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STM32F373xx Pinouts and pin description Table 11.
PAGE 36
Pinouts and pin description STM32F373xx Table 11.
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STM32F373xx Pinouts and pin description Table 11.
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Pinouts and pin description STM32F373xx Table 11.
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STM32F373xx Pinouts and pin description Table 11.
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Pinouts and pin description STM32F373xx Table 11.
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/137 Downloaded from Arrow.com.
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/137 Downloaded from Arrow.com. - - TIM2_ CH1_ETR SWCLK -JTCK JTDI PA14 PA15 AF3 TSC_ SYNC TSC_ G4_IO4 TIM5_ TSC_ CH4 G4_IO3 TIM16_ CH1N SWDIO -JTMS PA13 AF2 AF1 AF0 Pin Name I2C1_ SCL I2C1_ SDA - AF4 SPI1_NSS/ I2S1_WS - IR-OUT AF5 AF7 SPI3_NSS/ I2S3_WS - - SPI1_MISO USART3_CTS /I2S1_MCK AF6 - - - AF8 Table 12.
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/137 Downloaded from Arrow.com.
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- - - - - - - - - - - - - - - - PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 AF0 PC0 Pin Name 44/137 Downloaded from Arrow.com.
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/137 Downloaded from Arrow.com.
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/137 Downloaded from Arrow.com.
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/137 Downloaded from Arrow.com. - - - - - - - - PF1 PF2 PF4 PF6 PF7 PF9 PF10 AF0 PF0 Pin Name EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT - - AF1 - TIM14_CH1 - TIM4_CH4 - - - - AF2 - - - - - - - - AF3 - - I2C2_SDA I2C2_SCL - I2C2_SMBA I2C2_SCL I2C2_SDA AF4 - - - SPI1_MOSI/I2S1_SD - - - - AF5 Table 17.
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Memory mapping 5 STM32F373xx Memory mapping Figure 6. STM32F373xx memory map [)))) )))) [ )) &RUWH[ 0 LQWHUQDO SHULSKHUDOV [( $+% [ 5HVHUYHG [ )) $+% [ 5HVHUYHG [& [ & $3% [ 5HVHUYHG [$ [ $ $3% [ [ [ ))) )))) [ 2SWLRQ E\WHV [ ))) ) 6\VWHP PHPRU\ [ ))) ' [ 3HULSKHUDOV 5HVHUYHG [ [ 65$0 )ODVK PHPRU\ [
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STM32F373xx Memory mapping Table 18.
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Memory mapping STM32F373xx Table 18. STM32F373xx peripheral register boundary addresses(1) (continued) Bus APB2 - APB1 50/137 Downloaded from Arrow.com.
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STM32F373xx Memory mapping Table 18.
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Electrical characteristics STM32F373xx 6 Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range).
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STM32F373xx 6.1.6 Electrical characteristics Power supply scheme Figure 9. Power supply scheme 9%$7 %DFNXS FLUFXLWU\ /6( 57& :DNHXS ORJLF %DFNXS UHJLVWHUV /HYHO VKLIWHU 3R ZHU VZL WFK 9 287 *3 , 2V #9'' ,1 ,2 /RJLF 9'' î 9'' î Q) î ) 5HJXODWRU 9 .
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Electrical characteristics STM32F373xx Caution: Each power supply pair (VDD/VSS, VDDA/VSSA etc..) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure the good functionality of the device. 6.1.7 Current consumption measurement Figure 10.
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STM32F373xx 6.2 Electrical characteristics Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 19: Voltage characteristics, Table 20: Current characteristics, and Table 21: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 19.
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Electrical characteristics STM32F373xx The following relationship must be respected between VREFSD+ and VDDSD12, VDDSD3: VREFSD+ must be lower than VDDSD3. Depending on the SDADCx operation mode, there can be more constraints between VREFSD+, VDDSD12 and VDDSD3 which are described in reference manual RM0313. Table 20. Current characteristics Symbol Ratings Max.
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STM32F373xx Electrical characteristics 6.3 Operating conditions 6.3.1 General operating conditions Table 22. General operating conditions Symbol Parameter Conditions Min Max fHCLK Internal AHB clock frequency - 0 72 fPCLK1 Internal APB1 clock frequency - 0 36 fPCLK2 Internal APB2 clock frequency - 0 72 VDD Standard operating voltage Must have a potential equal to or lower than VDDA 2.0 3.6 2.4 3.6 2.0 3.6 2.2 3.6 2.0 3.6 2.2 3.6 2.0 3.6 2.4 3.6 2.0 3.
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Electrical characteristics STM32F373xx Table 22. General operating conditions (continued) Symbol Parameter Conditions Min Max Ambient temperature for 6 suffix version Maximum power dissipation –40 85 Low power dissipation(5) –40 105 Ambient temperature for 7 suffix version Maximum power dissipation –40 105 –40 125 6 suffix version –40 105 7 suffix version –40 125 TA TJ Junction temperature range Low power dissipation (5) Unit °C °C °C 1.
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STM32F373xx 6.3.3 Electrical characteristics Embedded reset and power control block characteristics The parameters given in Table 24 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 22. Table 24. Embedded reset and power control block characteristics Symbol Parameter VPOR/PDR(1) VPDRhyst (3) tRSTTEMPO (3) Power on/power down reset threshold Conditions Min Falling edge Rising edge Typ Max Unit 1.80(2) 1.88 1.96 V 1.84 1.
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Electrical characteristics 6.3.4 STM32F373xx Embedded reference voltage The parameters given in Table 27 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 22. Table 26. Embedded internal reference voltage calibration values Calibration value name Description Memory address Raw data acquired at temperature of 30 °C VDDA= 3.3 V VREFINT_CAL 0x1FFF F7BA - 0x1FFF F7BB Table 27.
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STM32F373xx 6.3.5 Electrical characteristics Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 10: Current consumption measurement scheme.
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Electrical characteristics STM32F373xx Table 28. Typical and maximum current consumption from VDD supply at VDD = 3.6 V(1) All peripherals enabled Symbol Parameter Conditions fHCLK Max @ TA(2) Typ 25 °C 72 MHz HSE bypass, PLL on Supply current in Run mode, code executing from RAM HSE bypass, PLL off HSI clock, PLL on HSI clock, PLL off IDD HSE bypass, PLL on Supply current in Sleep mode, code executing from Flash or RAM HSE bypass, PLL off HSI clock, PLL on HSI clock, PLL off 1. 63.
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STM32F373xx Electrical characteristics Table 29. Typical and maximum current consumption from VDDA supply VDDA= 2.
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Electrical characteristics STM32F373xx Table 31. Typical and maximum VDDA consumption in Stop and Standby modes Parameter Supply current in Stop mode IDDA Supply current in Standby mode Supply current for IDDAmon VDDA and VDDSD12 monitoring Max(1) 2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V TA= TA= TA= 25 °C 85 °C 105 °C Conditions VDDA and VDDSD12 Symbol Typ@VDD (VDD=VDDA) Regulator in run mode, all 1.99 oscillators OFF 2.07 2.19 2.33 2.46 2.64 10.8 11.8 12.4 Regulator in low-power 1.
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STM32F373xx Electrical characteristics Figure 11. Typical VBAT current consumption (LSE and RTC ON/LSEDRV[1:0]='00') 9 ) 6"!4 ! 9 9 9 9 9 9 9 & & & & 4! # -3 6 Typical current consumption The MCU is placed under the following conditions: • VDD = VDDA = VDDSD12 = VDDSD3 = 3.
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Electrical characteristics STM32F373xx Table 33.
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STM32F373xx Electrical characteristics Table 34.
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Electrical characteristics STM32F373xx I/O system current consumption The current consumption of the I/O system has two components: static and dynamic. I/O static current consumption All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 52: I/O static characteristics.
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STM32F373xx Electrical characteristics Table 35. Switching output I/O current consumption Symbol Parameter Conditions(1) VDD = 3.3 V Cext = 0 pF C = CINT + CEXT+ CS VDD = 3.3 V Cext = 10 pF C = CINT + CEXT+ CS ISW I/O current consumption VDD = 3.3 V Cext = 22 pF C = CINT + CEXT+ CS VDD = 3.3 V Cext = 33 pF C = CINT + CEXT+ CS VDD = 3.3 V Cext = 47 pF C = CINT + CEXT+ CS I/O toggling frequency (fSW) Typ 2 MHz 0.77 4 MHz 0.87 8 MHz 0.95 18 MHz 1.59 36 MHz 2.57 48 MHz 3.11 2 MHz 0.
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Electrical characteristics STM32F373xx On-chip peripheral current consumption The MCU is placed under the following conditions: • All I/O pins are in analog input configuration. • All peripherals are disabled unless otherwise mentioned. • The given value is calculated by measuring the current consumption • – with all peripherals clocked off; – with only one peripheral clocked on. Ambient operating temperature at 25°C and VDD = VDDA= 3.3 Volts. Table 36.
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STM32F373xx Electrical characteristics Table 36. Peripheral current consumption (continued) Typical consumption(1) Peripheral Unit APB1 peripherals APB1-Bridge(3) 6.9 TIM2 47.9 TIM3 36.8 TIM4 36.9 TIM5 45.5 TIM6 8.4 TIM7 8.2 TIM12 21.3 TIM13 14.2 TIM14 14.4 TIM18 10.1 WWDG 4.7 SPI2 24.3 SPI3 25.3 USART2 45.3 USART3 43.1 I2C1 14.0 I2C2 13.9 USB 27.9 CAN 38.1 DAC2 7.7 PWR 5.4 DAC1 14.8 CEC 5.4 µA/MHz 1.
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Electrical characteristics STM32F373xx All timings are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 22. Table 37. Low-power mode wakeup timings Symbol Parameter Typ @VDD = VDDA Conditions = 2.0 V = 2.4 V = 2.7 V tWUSTOP tWUSTANDB Y tWUSLEEP 6.3.7 Wakeup from Stop mode Wakeup from Standby mode Max =3V = 3.3 V Regulator in run mode 4.1 3.9 3.8 3.7 3.6 4.5 Regulator in low power mode 7.9 6.7 6.1 5.7 5.4 8.
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STM32F373xx Electrical characteristics Figure 12. High-speed external clock source AC timing diagram WZ +6(+ 9+6(+ 9+6(/ WU +6( WI +6( W WZ +6(/ 7+6( 06 9 Low-speed external user clock generated from an external source In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal has to respect the I/O characteristics in Section 6.3.14. However, the recommended clock input waveform is shown in Figure 13. Table 39.
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Electrical characteristics STM32F373xx Figure 13. Low-speed external clock source AC timing diagram WZ /6(+ 9/6(+ 9/6(/ WU /6( WI /6( W WZ /6(/ 7/6( 06 9 High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 32 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 40.
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STM32F373xx Electrical characteristics For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 20 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 14). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2.
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Electrical characteristics STM32F373xx Low-speed external clock generated from a crystal resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 41.
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STM32F373xx Electrical characteristics Figure 15. Typical application with a 32.768 kHz crystal 5HVRQDWRU ZLWK LQWHJUDWHG FDSDFLWRUV &/ I/6( 26& B,1 'ULYH SURJUDPPDEOH DPSOLILHU N+ ] UHVRQDWRU 26& B28 7 &/ 06 9 Note: An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one. 6.3.
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Electrical characteristics STM32F373xx Figure 16. HSI oscillator accuracy characterization results -!8 -). 4! ; #= -3 6 Low-speed internal (LSI) RC oscillator Table 43. LSI oscillator characteristics(1) Symbol fLSI tsu(LSI) Parameter Min Typ Max Unit 30 40 60 kHz LSI oscillator startup time - - 85 µs LSI oscillator power consumption - 0.75 1.2 µA Frequency (2) IDD(LSI)(2) 1. VDDA = 3.
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STM32F373xx 6.3.10 Electrical characteristics Memory characteristics Flash memory The characteristics are given at TA = –40 to 105 °C unless otherwise specified. Table 45. Flash memory characteristics Min Typ Max(1) Unit 16-bit programming time TA = –40 to +105 °C 40 53.
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Electrical characteristics 6.3.11 STM32F373xx EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs.
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STM32F373xx Electrical characteristics To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports).
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Electrical characteristics STM32F373xx Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: • A supply overvoltage is applied to each power supply pin • A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78A IC latch-up standard. Table 50. Electrical sensitivities Symbol LU 6.3.
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STM32F373xx Electrical characteristics Table 51.
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Electrical characteristics 6.3.14 STM32F373xx I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 52 are derived from tests performed under the conditions summarized in Table 22. All I/Os are CMOS and TTL compliant. Table 52. I/O static characteristics (1) Symbol VIL Parameter Low level input voltage Conditions High level input voltage Vhys Ilkg Input leakage current (3) Max Unit (2) - - 0.3VDD+0.
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STM32F373xx Note: Electrical characteristics I/O pins are powered from VDD voltage except pins which can be used as SDADC inputs: - The PB2, PB10 and PE7 to PE15 I/O pins are powered from VDDSD12. - PB14 to PB15 and PD8 to PD15 I/O pins are powered from VDDSD3. All I/O pin ground is internally connected to VSS. VDD mentioned in the Table 52 represents power voltage for a given I/O pin (VDD or VDDSD12 or VDDSD3). All I/Os are CMOS and TTL compliant (no software configuration required).
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Electrical characteristics STM32F373xx Figure 18.
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STM32F373xx Electrical characteristics Output voltage levels Unless otherwise specified, the parameters given in Table 53 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 22. All I/Os are CMOS and TTL compliant (FT, TTa or TC unless otherwise specified). Table 53.
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Electrical characteristics STM32F373xx Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 19 and Table 54, respectively. Unless otherwise specified, the parameters given are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 22. Table 54.
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STM32F373xx Electrical characteristics Figure 19. I/O AC characteristics definition (;7(51$/ 287387 21 S) W I ,2 RXW W U ,2 RXW 7 0D[LPXP IUHTXHQF\ LV DFKLHYHG LI W W U I 7 DQG LI WKH GXW\ F\FOH LV ZKHQ ORDGHG E\ S) 06 9 6.3.15 NRST characteristics NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 52).
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Electrical characteristics STM32F373xx Figure 20. Recommended NRST pin protection 9'' ([WHUQDO UHVHW FLUFXLWU\ 538 1567 ,QWHUQDO UHVHW )LOWHU ) 06 9 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 55. Otherwise the reset will not be taken into account by the device. 90/137 Downloaded from Arrow.com.
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STM32F373xx 6.3.16 Electrical characteristics Communications interfaces I2C interface characteristics The I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” opendrain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The I2C characteristics are described in Table 56. Refer also to Section 6.3.
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Electrical characteristics STM32F373xx Table 57. I2C analog filter characteristics(1) Symbol Parameter Min Max Unit tAF Maximum pulse width of spikes that are suppressed by the analog filter 50(2) 260(3) ns 1. Guaranteed by design. 2. Spikes width below tAF(min) are filtered. 3. Spikes width above tAF(max) are not filtered. Figure 21.
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STM32F373xx Electrical characteristics SPI/I2S characteristics Unless otherwise specified, the parameters given in Table 58 for SPI or in Table 59 for I2S are derived from tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 22. Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S). Table 58.
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Electrical characteristics STM32F373xx Figure 22. SPI timing diagram - slave mode and CPHA = 0 166 LQSXW 6&. ,QSXW W68 166 &3+$ &32/ &3+$ &32/ WK 166 WF 6&. WZ 6&.+ WZ 6&./ W9 62 WD 62 0,62 287387 WU 6&. WI 6&. WK 62 06% 287 %,7 287 06% ,1 %,7 ,1 WGLV 62 /6% 287 WVX 6, 026, ,1387 /6% ,1 WK 6, DL F Figure 23. SPI timing diagram - slave mode and CPHA = 1(1) 166 LQSXW 6&. LQSXW W68 166 &3+$ &32/ &3+$ &32/ WZ 6&.+ WZ 6&.
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STM32F373xx Electrical characteristics Figure 24. SPI timing diagram - master mode(1) +LJK 166 LQSXW 6&. 2XWSXW &3+$ &32/ 6&. 2XWSXW WF 6&. &3+$ &32/ &3+$ &32/ &3+$ &32/ WVX 0, 0,62 ,13 87 WZ 6&.+ WZ 6&./ 06% ,1 WU 6&. WI 6&. %,7 ,1 /6% ,1 WK 0, 026, 287387 06% 287 WY 02 % , 7 287 /6% 287 WK 02 DL F 1. Measurement points are done at 0.5VDD level and with external CL = 30 pF. DocID022691 Rev 7 95/137 114 Downloaded from Arrow.com.
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Electrical characteristics STM32F373xx Table 59. I2S characteristics Symbol Parameter Conditions Min Max Unit 30 70 % 1.528 1.539 Slave mode 0 12.
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STM32F373xx Electrical characteristics Figure 25. I2S slave timing diagram (Philips protocol)(1) &. ,QSXW WF &. &32/ &32/ WZ &.+ WK :6 WZ &./ :6 LQSXW WY 6'B67 WVX :6 6'WUDQVPLW /6% WUDQVPLW 06% WUDQVPLW WVX 6'B65 /6% UHFHLYH 6'UHFHLYH WK 6'B67 %LWQ WUDQVPLW /6% WUDQVPLW WK 6'B65 06% UHFHLYH %LWQ UHFHLYH /6% UHFHLYH DL E 1. Measurement points are done at 0.5 VDD level and with external CL = 30 pF. 2. LSB transmit/receive of the previously transmitted byte.
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Electrical characteristics 6.3.17 STM32F373xx 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 60 are preliminary values derived from tests performed under ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 22. Note: It is recommended to perform a calibration after each power-up. Table 60. ADC characteristics Symbol Parameter Conditions Min Typ Max Unit VDDA Power supply - 2.4 - 3.
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STM32F373xx Electrical characteristics Equation 1: RSRC max formula TS - – R ADC R SRC < --------------------------------------------------------------N+2 f ADC × C ADC × ln ( 2 ) The formula above (Equation 1) is used to determine the maximum external signal source impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution). Table 61. RSRC max for fADC = 14 MHz(1) Ts (cycles) tS (µs) RSRC max (kΩ) 1.5 0.11 0.4 7.5 0.54 5.9 13.5 0.96 11.4 28.5 2.04 25.2 41.5 2.
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Electrical characteristics STM32F373xx 2. ADC accuracy vs. negative injection current: Injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.
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STM32F373xx 6.3.18 Electrical characteristics DAC electrical specifications Table 63. DAC characteristics Symbol Parameter Conditions Min Typ Max Unit 2.4 - 3.6 V 2.4 - 3.
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Electrical characteristics STM32F373xx Table 63. DAC characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit - - - ±10 mV Given for the DAC in 10-bit at VREF+ = 3.6 V - - ±3 LSB Given for the DAC in 12-bit at VREF+ = 3.6 V - - ±12 LSB Given for the DAC in 12bit configuration - - ±0.
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STM32F373xx 6.3.19 Electrical characteristics Comparator characteristics Table 64. Comparator characteristics Symbol VDDA Parameter Conditions Min Typ Max(1) Unit Analog supply voltage - 2 - 3.6 V VIN Comparator input voltage range - 0 - VDDA V VBG VREFINT scaler input voltage - - 1.
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Electrical characteristics STM32F373xx Table 64. Comparator characteristics (continued) Symbol Parameter Conditions Min Typ No hysteresis (COMPxHYST[1:0]=00) Low hysteresis (COMPxHYST[1:0]=01) Vhys Comparator hysteresis Medium hysteresis (COMPxHYST[1:0]=10) High hysteresis (COMPxHYST[1:0]=11) - - High speed mode 3 All other power modes 5 High speed mode 7 All other power modes 9 High speed mode 18 All other power modes 19 Max(1) 0 Unit 13 8 10 mV 26 15 19 49 31 40 1.
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STM32F373xx 6.3.20 Electrical characteristics Temperature sensor characteristics Table 65. Temperature sensor calibration values Calibration value name Description Memory address TS_CAL1 TS ADC raw data acquired at temperature of 30 °C ± 5 °C, VDDA= 3.3 V 0x1FFF F7B8 - 0x1FFF F7B9 TS_CAL2 TS ADC raw data acquired at temperature of 110 °C ± 5 °C VDDA= 3.3 V 0x1FFF F7C2 - 0x1FFF F7C3 Table 66.
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Electrical characteristics STM32F373xx Table 68. TIMx(1) (2)characteristics Symbol tres(TIM) Parameter Timer resolution time Conditions Min Max Unit - 1 - tTIMxCLK fTIMxCLK = 72 MHz 13.9 - ns 0 fTIMxCLK/2 MHz 0 24 MHz TIMx (except TIM2) - 16 TIM2 - 32 - 1 65536 tTIMxCLK fTIMxCLK = 72 MHz 0.0139 910 µs - - 65536 × 65536 tTIMxCLK fTIMxCLK = 72 MHz - 59.
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STM32F373xx 6.3.23 Electrical characteristics USB characteristics Table 71. USB startup time Symbol tSTARTUP(1) Parameter USB transceiver startup time Max Unit 1 µs 1. Guaranteed by design. Table 72. USB DC electrical characteristics Symbol Parameter Conditions Min.(1) Max.(1) Unit - 3.0(3) 3.6 V I(USB_DP, USB_DM) 0.2 - Input levels VDD USB operating voltage(2) VDI(4) Differential input sensitivity (for USB compliance) VCM(4) Differential common mode range Includes VDI range 0.
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Electrical characteristics STM32F373xx Figure 31. USB timings: definition of data signal rise and fall time &URVVRYHU SRLQWV 'LIIHUHQWLDO GDWD OLQHV 9&56 966 WU WI DL Table 73. USB: Full-speed electrical characteristics(1) Symbol Parameter Conditions Min Typ Max Unit CL = 50 pF 4 - 20 ns CL = 50 pF 4 - 20 ns tr/tf 90 - 110 % - 1.3 - 2.
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STM32F373xx Electrical characteristics Table 74. SDADC characteristics (continued)(1) Symbol VREFSD- IDDSDx VAIN Parameter Conditions Min Typ Max Unit Note Negative ref. voltage - - VSSA - V - Normal mode (fADC = 6 MHz) - 800 1200 - Slow mode (fADC = 1.5 MHz) - - 600 - Standby - - 200 Power down - - 2.5 - SD_ADC off - - 1 - VREFSD- - VREFSD+ /gain VREFSD- - VREFSD+/ (gain*2) VSSA - VDDSDx Supply current (VDDSDx = 3.
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Electrical characteristics STM32F373xx Table 74. SDADC characteristics (continued)(1) Symbol Parameter Conditions Dvoffsettem p gain = 1 gain = 8 fADC = 6 MHz fADC = 6 MHz Typ Max VREFSD+ = 3.3 - - 110 VREFSD+ = 1.2 - - 110 VREFSD+ = 3.3 - - 100 VREFSD+ = 1.2 - - 70 VREFSD+ = 3.3 - - 100 VDDSDx = 3.3 fADC = VREFSD+ 1.5 MHz = 3.3 gain = 1 Offset error Single ended mode EO gain = 8 Differential mode fADC = 1.5 MHz Min - - 90 VREFSD+ = 1.2 - - 2100 VREFSD+ = 3.
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STM32F373xx Electrical characteristics Table 74. SDADC characteristics (continued)(1) Conditions gain = 8 gain = 8 gain = 1 gain = 8 Differential mode gain = 8 gain = 1 VDDSDx = 3.3 Single ended mode ED Differential linearity error gain = 1 VDDSDx = 3.3 Single ended mode EL Integral linearity error(2) gain = 1 Parameter Differential mode Symbol Min Typ Max VREFSD+ = 1.2 - - 16 VREFSD+ = 3.3 - - 14 VREFSD+ = 1.2 - - 26 VREFSD+ = 3.3 - - 14 VREFSD+ = 1.
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Electrical characteristics STM32F373xx Table 74. SDADC characteristics (continued)(1) Symbol Parameter Conditions Min Typ Max VREFSD+ = 3.3(3) 84 85 - VREFSD+ = 1.2(4) 86 88 - VREFSD+ = 3.3 88 92 - VREFSD+ = 1.2(4) 76 78 - VREFSD+ = 3.3 82 86 - fADC = VDDSDx VREFSD+ 1.5 MHz = 3.3 = 3.3(3) 76 80 - fADC = 1.5 MHz VREFSD+ = 3.3 80 84 - VREFSD+ = 1.2(4) 77 81 - VREFSD+ = 3.3 85 90 - VREFSD+ = 1.2(4) 66 71 - VREFSD+ = 3.
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STM32F373xx Electrical characteristics Table 74. SDADC characteristics (continued)(1) Symbol Parameter Conditions Min Typ Max VREFSD+ = 3.3(3) 76 77 - VREFSD+ = 1.2(4) 75 76 - VREFSD+ = 3.3 76 77 - VREFSD+ = 1.2(4) 70 74 - VREFSD+ = 3.3 79 85 - fADC = VDDSDx VREFSD+ 1.5 MHz = 3.3 = 3.3(3) 75 81 - fADC = 1.5MHz VREFSD+ = 3.3 72 73 - VREFSD+ = 1.2(4) 68 71 - VREFSD+ = 3.3 72 73 - VREFSD+ = 1.2(4) 60 64 - VREF = 3.3 67 72 - VREFSD+ = 3.
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Electrical characteristics STM32F373xx 1. Guaranteed by characterization results. 2. Integral linearity error can be improved by software calibration of SDADC transfer curve (2-nd order polynomial calibration). 3. For fADC lower than 5 MHz, there will be a performance degradation of around 2 dB due to flicker noise increase. 4. If the reference value is lower than 2.4 V, there will be a performance degradation proportional to the reference supply drop, according to this formula: 20*log10(VREF/2.4) dB 5.
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STM32F373xx 7 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 7.1 UFBGA100 package information Figure 32. UFBGA100 - 100-pin, 7 x 7 mm, 0.
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Package information STM32F373xx Table 76. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. D 6.950 7.000 7.050 0.2736 0.2756 0.2776 D1 5.450 5.500 5.550 0.2146 0.2165 0.2185 E 6.950 7.000 7.050 0.2736 0.2756 0.2776 E1 5.450 5.500 5.550 0.2146 0.2165 0.2185 e - 0.500 - - 0.0197 - F 0.700 0.750 0.800 0.0276 0.0295 0.0315 ddd - - 0.
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STM32F373xx Package information Device Marking for UFBGA100 The following figure gives an example of topside marking orientation versus ball 1 identifier location. Figure 34. UFBGA100 marking example (package top view) WƌŽĚƵĐƚ ŝĚĞŶƚŝĨŝĐĂƚŝŽŶ;ϭͿ ϯϮ&ϯϳϯ sϴ,ϲ ĂƚĞ ĐŽĚĞ с ǇĞĂƌ н ǁĞĞŬ z tt Ăůů ϭ ŝĚĞŶƚŝĨŝĐĂƚŝŽŶ ĚĚŝƚŝŽŶĂů ŝŶĨŽƌŵĂƚŝŽŶ 06Y 9 1.
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Package information 7.2 STM32F373xx LQFP100 package information Figure 35. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline MM C ! ! ! 3%!4).' 0,!.% # '!5'% 0,!.% $ , $ ! + CCC # , $ 0). )$%.4)&)#!4)/. E 1. Drawing is not to scale. 118/137 Downloaded from Arrow.com.
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STM32F373xx Package information Table 78. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 15.800 16.000 16.200 0.6220 0.6299 0.6378 D1 13.800 14.000 14.200 0.5433 0.5512 0.5591 D3 - 12.000 - - 0.
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Package information STM32F373xx Figure 36. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat recommended footprint AI C 1. Dimensions are expressed in millimeters. Device marking for LQFP100 The following figure gives an example of topside marking orientation versus pin 1 identifier location. Figure 37.
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STM32F373xx 7.3 Package information LQFP64 package information Figure 38. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline PP *$8*( 3/$1( F $ $ $ 6($7,1* 3/$1( & $ FFF & ' ' ' . / / 3,1 ,'(17,),&$7,21 ( ( ( E H :B0(B9 1. Drawing is not to scale. DocID022691 Rev 7 121/137 130 Downloaded from Arrow.com.
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Package information STM32F373xx Table 79. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D - 12.000 - - 0.4724 - D1 - 10.000 - - 0.3937 - D3 - 7.500 - - 0.2953 - E - 12.000 - - 0.
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STM32F373xx Package information Figure 39. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package recommended footprint AI C 1. Dimensions are expressed in millimeters. Device marking for LQFP64 The following figure gives an example of topside marking orientation versus pin 1 identifier location. Figure 40.
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Package information 7.4 STM32F373xx LQFP48 package information Figure 41. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline C ! ! ! 3%!4).' 0,!.% # MM '!5'% 0,!.% CCC # + ! $ $ , , $ 0). )$%.4)&)#!4)/. 1. Drawing is not to scale. Downloaded from Arrow.com.
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STM32F373xx Package information Table 80. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 8.800 9.000 9.200 0.3465 0.3543 0.3622 D1 6.800 7.000 7.200 0.2677 0.2756 0.2835 D3 - 5.500 - - 0.
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Package information STM32F373xx Figure 42. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package recommended footprint AI D 1. Dimensions are expressed in millimeters. Device marking for LQFP48 The following figure gives an example of topside marking orientation versus pin 1 identifier location. Figure 43.
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STM32F373xx 7.5 Package information Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 22: General operating conditions.
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Package information 7.5.2 STM32F373xx Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Section 8: Part numbering. Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature.
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STM32F373xx Package information Using the values obtained in Table 81 TJmax is calculated as follows: – For LQFP100, 46°C/W TJmax = 115 °C + (46°C/W × 98.8 mW) = 115 °C + 4.54 °C = 119.5 °C This is within the range of the suffix 7 version parts (–40 < TJ < 125 °C). In this case, parts must be ordered at least with the temperature range suffix 7 (see Section 8: Part numbering). Figure 44. LQFP64 PD max vs.
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Part numbering 8 STM32F373xx Part numbering For a list of available options (memory, package, and so on) or for further information on any aspect of this device, please contact your nearest ST sales office. Table 82.
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STM32F373xx 9 Revision history Revision history Table 83. Document revision history Date Revision 18-Jun-2012 1 Initial release. 2 Added ‘F’ to all ‘Cortex-M4’ occurrences Modified the shapes of Figure 2: STM32F373xx LQFP48 pinout to Figure 4: STM32F373xx LQFP100 pinout Added two rows ‘VREFSD+ - VDDSD3’ and ‘VREF+ - VDDA’ in Table 19: Voltage characteristics Removed PB0 in footnote of Table 19: Voltage characteristics and in Section 6.3.14: I/O port characteristics Added a paragraph after ‘...
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Revision history STM32F373xx Table 83. Document revision history (continued) Date 07-Sep-2012 132/137 Downloaded from Arrow.com.
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STM32F373xx Revision history Table 83. Document revision history (continued) Date 21-Dec-2012 Revision Changes 3 Updated Table 2: Device overview, capacitive sensing channels peripheral added. Updated Table 3: Capacitive sensing GPIOs available on STM32F373xx devices Updated Section 3.
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Revision history STM32F373xx Table 83. Document revision history (continued) Date 19-Sep-2013 134/137 Downloaded from Arrow.com. Revision Changes 4 Replaced “Cortex-M4F” with “Cortex-M4” throughout the document. Removed part number STM32F372xx. Added “1.25 DMIPS/MHz (Dhrystone 2.1)” in Features. Updated Introduction. Added reference to the STMTouch touch sensing firmware library in Section 3.16: Touch sensing controller (TSC). Added “All I2S interfaces can operate in half-duplex mode only.
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STM32F373xx Revision history Table 83. Document revision history (continued) Date 18-Mar-2014 Revision 5 Changes Renamed part number STM32F37x to STM32F373xx Added note1 in Table 28: Typical and maximum current consumption from VDD supply at VDD = 3.6 V Updated Chapter 3.14: Digital-to-analog converter (DAC) Updated, added note 2 and 3 in Table 57: I2C analog filter characteristics Renamed tSP symbol with tAF.
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Revision history STM32F373xx Table 83. Document revision history (continued) Date 08-Jun-2016 136/137 Downloaded from Arrow.com. Revision Changes 7 Updated: – Table 3: Capacitive sensing GPIOs available on STM32F373xx devices – Table 19: Voltage characteristics – Table 27: Embedded internal reference voltage – Table 41: LSE oscillator characteristics (fLSE = 32.
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STM32F373xx IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.