Datasheet

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STM32F334x4 STM32F334x6 STM32F334x8 Electrical characteristics
101
SPI characteristics
Unless otherwise specified, the parameters given in Table 53 for SPI are derived from tests
performed under ambient temperature, f
PCLKx
frequency and V
DD
supply voltage conditions
summarized in
Table 19: General operating conditions.
Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).
Table 62. I
2
C analog filter characteristics
(1)
1. Guaranteed by design, not tested in production.
Symbol Parameter Min. Max. Unit
t
AF
Maximum pulse width of spikes that are
suppressed by the analog filter.
50
(2)
2. Spikes with width below t
AF
(min.) are filtered.
260
(3)
3. Spikes with width above t
AF
(max.) are not filtered.
ns
Table 63. SPI characteristics
(1)
Symbol Parameter Conditions Min. Typ. Max. Unit
f
SCK
1/t
c(SCK)
SPI clock frequency
Master mode 2.7 < V
DD
< 3.6 V
--
24
MHz
Master mode 2 < V
DD
< 3.6 V 18
Slave mode 2 < V
DD
< 3.6 V 24
Slave mode transmitter/full
duplex
2 < V
DD
< 3.6 V
18
(2)
DuCy(SCK)
Duty cycle of SPI clock
frequency
Slave mode 30 50 70 %
t
su(NSS)
NSS setup time Slave mode, SPI presc = 2 4*Tpclk - -
ns
t
h(NSS)
NSS hold time Slave mode, SPI presc = 2 2*Tpclk - -
t
w(SCKH)
t
w(SCKL)
SCK high and low time Master mode Tpclk-2 Tpclk Tpclk+2
t
su(MI)
Data input setup time
Master mode 0 - -
t
su(SI)
Slave mode 3 - -
t
h(MI)
Data input hold time
Master mode 5 - -
t
h(SI)
Slave mode 1 - -
t
a(SO)
Data output access time Slave mode 10 - 40
t
dis(SO)
Data output disable time Slave mode 10 - 17
t
v(SO)
Data output valid time
Slave mode 2.7 < V
DD
< 3.6 V - 12 20
Slave mode 2 < V
DD
< 3.6 V - 12 27.5
t
v(MO)
Master mode - 1.5 5
t
h(SO)
Data output hold time
Slave mode 7.5 - -
t
h(MO)
Master mode 0 - -
1. Data based on characterization results, not tested in production.
2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK
low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a
master having tsu(MI) = 0 while Duty(SCK) = 50%.
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