Datasheet

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STM32F334x4 STM32F334x6 STM32F334x8 Functional overview
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3.14.1 217 ps high-resolution timer (HRTIM1)
The high-resolution timer (HRTIM1) allows generating digital signals with high-accuracy
timings, such as PWM or phase-shifted pulses.
It consists of 6 timers, 1 master and 5 slaves, totaling 10 high-resolution outputs, which can
be coupled by pairs for deadtime insertion. It also features 5 fault inputs for protection
purposes and 10 inputs to handle external events such as current limitation, zero voltage or
zero current switching.
HRTIM1 timer is made of a digital kernel clocked at 144 MHz followed by delay lines. Delay
lines with closed loop control guarantee a 217
ps resolution whatever the voltage,
temperature or chip-to-chip manufacturing process deviation. The high-resolution is
available on the 10 outputs in all operating modes: variable duty cycle, variable frequency,
and constant ON time.
The slave timers can be combined to control multiswitch complex converters or operate
independently to manage multiple independent converters.
The waveforms are defined by a combination of user-defined timings and external events
such as analog or digital feedbacks signals.
HRTIM1 timer includes options for blanking and filtering out spurious events or faults. It also
offers specific modes and features to offload the CPU: DMA requests, burst mode controller,
push-pull and resonant mode.
It supports many topologies including LLC, Full bridge phase shifted, buck or boost
converters, either in voltage or current mode, as well as lighting application (fluorescent or
LED). It can also be used as a general purpose timer, for instance to achieve high-resolution
PWM-emulated DAC.
In debug mode, the HRTIM1 counters can be frozen and the PWM outputs enter safe state.
3.14.2 Advanced timer (TIM1)
The advanced-control timer can be seen as a three-phase PWM multiplexed on 6 channels.
They have complementary PWM outputs with programmable inserted dead-times. They can
also be seen as complete general-purpose timers. The 4 independent channels can be
used for:
• Input capture
• Output compare
• PWM generation (edge or center-aligned modes) with full modulation capability
(0-100%)
• One-pulse mode output
In debug mode, the advanced-control timer counter can be frozen and the PWM outputs
disabled to turn off any power switches driven by these outputs.
Many features are shared with those of the general-purpose TIM timers (described in
Section 3.14.3) using the same architecture, so the advanced-control timers can work
together with the TIM timers via the Timer Link feature for synchronization or event chaining.
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