Datasheet

ManualsBrandsST ManualsEmbedded Processors & ControllersMicrocontroller 32bit 64KB LQFP

This is information on a product in full production.

December 2017 DocID025409 Rev 8 1/121

STM32F334x4 STM32F334x6

STM32F334x8

Arm

Cortex

-M4 32b MCU+FPU,up to 64KB Flash,16KB SRAM,

2 ADCs,3 DACs,3 comp.,op-amp, 217ps 10-ch (HRTIM1)

Datasheet - production data

Features

• Core: Arm

Cortex

-M4 32-bit CPU with FPU

(72 MHz max), single-cycle multiplication and

HW division DSP instruction

• Memories

– Up to 64 Kbytes of Flash memory

– Up to 12 Kbytes of SRAM with HW parity

check

– Routine booster: 4 Kbytes of SRAM on

instruction and data bus with HW parity

check (CCM)

• CRC calculation unit

• Reset and supply management

–V

DD,

DDA

voltage range: 2.0 to 3.6 V

– Power-on/Power-down reset (POR/PDR)

– Programmable voltage detector (PVD)

– Low-power modes: Sleep, Stop, Standby

–V

BAT

supply for RTC and backup registers

• Clock management

– 4 to 32 MHz crystal oscillator

– 32 kHz oscillator for RTC with calibration

– Internal 8 MHz RC (up to 64 MHz with PLL

option)

– Internal 40 kHz oscillator

• Up to 51 fast I/O ports, all mappable on

external interrupt vectors, several 5 V-tolerant

• Interconnect matrix

• 7-channel DMA controller

• Up to two ADC 0.20 µs (up to 21 channels) with

selectable resolution of 12/10/8/6 bits, 0 to

3.6 V conversion range, single-ended /

differential mode, separate analog supply from

2.0 to 3.6 V

• Temperature sensor

• Up to three 12-bit DAC channels with analog

supply from 2.4 V to 3.6 V

• Three ultra-fast rail-to-rail analog comparators

with analog supply from 2 to 3.6 V

• One operational amplifiers that can be used in

PGA mode, all terminals accessible with

analog supply from 2.4 to 3.6 V

• Up to 18 capacitive sensing channels

supporting touchkeys, linear and rotary touch

sensors

• Up to 12 timers

– HRTIM: 6 x16-bit counters, 217 ps

resolution, 10 PWM, 5 fault inputs, 10 ext

event input, 1 synchro. input,1 synchro. out

– One 32-bit timer and one 16-bit timer with

up to 4 IC/OC/PWM or pulse counter and

quadrature (incremental) encoder input

– One 16-bit 6-channel advanced-control

timer, with up to 6 PWM channels,

deadtime generation and emergency stop

– One 16-bit timer with 2 IC/OCs,

1 OCN/PWM, deadtime generation,

emergency stop

– Two 16-bit timers with IC/OC/OCN/PWM,

deadtime generation and emergency stop

– Two watchdog timers (independent,

window)

– SysTick timer: 24-bit downcounter

– Up to two 16-bit basic timers to drive DAC

• Calendar RTC with alarm, periodic wakeup

from Stop

• Communication interfaces

– CAN interface (2.0 B Active) and one SPI

LQFP32 (7 x 7 mm)

LQFP48 (7 x 7 mm)

LQFP64 (10 x 10 mm)

WLCSP49

(3.89x3.74 mm)

www.st.com

Downloaded from Arrow.com.

Summary of content (121 pages)

PAGE 1
STM32F334x4 STM32F334x6 STM32F334x8 Arm®Cortex®-M4 32b MCU+FPU,up to 64KB Flash,16KB SRAM, 2 ADCs,3 DACs,3 comp.,op-amp, 217ps 10-ch (HRTIM1) Datasheet - production data Features • Core: Arm® Cortex®-M4 32-bit CPU with FPU (72 MHz max), single-cycle multiplication and HW division DSP instruction LQFP32 (7 x 7 mm) LQFP48 (7 x 7 mm) LQFP64 (10 x 10 mm) • Memories – Up to 64 Kbytes of Flash memory WLCSP49 (3.89x3.
PAGE 2
STM32F334x4 STM32F334x6 STM32F334x8 – One I2C with 20 mA current sink to support Fast mode plus, SMBus/PMBus • Debug mode: serial wire debug (SWD), JTAG – Up to 3 USARTs, one with ISO/IEC 7816 interface, LIN, IrDA, modem control • All packages ECOPACK®2 compliant • 96-bit unique ID Table 1. Device summary 2/121 Downloaded from Arrow.com.
PAGE 3
STM32F334x4 STM32F334x6 STM32F334x8 Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 Arm® Cortex®-M4 core with FPU with embedded Flash memory and SRAM . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 4
Contents STM32F334x4 STM32F334x6 STM32F334x8 3.14.1 217 ps high-resolution timer (HRTIM1) . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.14.2 Advanced timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.14.3 General-purpose timers (TIM2, TIM3, TIM15, TIM16 and TIM17) . . . . . 24 3.14.4 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.14.5 Independent watchdog . . . . . . . . . . . . . . . . . . . . .
PAGE 5
STM32F334x4 STM32F334x6 STM32F334x8 7 Contents 6.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.3.6 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.3.8 Internal clock source characteristics . . . .
PAGE 6
List of tables STM32F334x4 STM32F334x6 STM32F334x8 List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45.
PAGE 7
STM32F334x4 STM32F334x6 STM32F334x8 Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. List of tables Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 8
List of figures STM32F334x4 STM32F334x6 STM32F334x8 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41.
PAGE 9
STM32F334x4 STM32F334x6 STM32F334x8 1 Introduction Introduction This datasheet provides the ordering information and the mechanical device characteristics of the STM32F334x4/6/8 microcontrollers. This document must be read in conjunction with the STM32F334xx, reference manual RM0364 available from the STMicroelectronics website www.st.com. For information on the Cortex®-M4 core with FPU, refer to: • Arm® Cortex®-M4 Processor Technical Reference Manual available from the www.arm.com website.
PAGE 10
Description 2 STM32F334x4 STM32F334x6 STM32F334x8 Description The STM32F334x4/6/8 family incorporates the high-performance Arm® Cortex®-M4 32-bit RISC core operating at up to 72 MHz frequency embedding a floating point unit (FPU), high-speed embedded memories (up to 64 Kbytes of Flash memory, up to 12 Kbytes of SRAM), and an extensive range of enhanced I/Os and peripherals connected to two APB buses.
PAGE 11
STM32F334x4 STM32F334x6 STM32F334x8 Description Table 2. STM32F334x4/6/8 family device features and peripheral counts (continued) Peripheral Comm.
PAGE 12
Description STM32F334x4 STM32F334x6 STM32F334x8 Figure 1. STM32F334x4/6/8 block diagram @VDD33 FPU Ibus CORTEX M4 CPU Dbus F max = 72MHz System bus NVIC BusMatrix JTRST JTDI JTCK-SWCLK JTMS-SWDAT JTDO-TRACESWO as AF Obl Flash interface TPIU SWJTAG Flash 64KB 64 bits VOLT. REG. 3.3V TO 1.8V V DD33 =2 to 3.
PAGE 13
STM32F334x4 STM32F334x6 STM32F334x8 Functional overview 3 Functional overview 3.1 Arm® Cortex®-M4 core with FPU with embedded Flash memory and SRAM The Arm Cortex-M4 processor with FPU is the latest generation of Arm processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts.
PAGE 14
Functional overview 3.2.3 STM32F334x4 STM32F334x6 STM32F334x8 Boot modes At startup, BOOT0 pin and BOOT1 option bit are used to select one of the three boot options: • Boot from user Flash memory • Boot from system memory • Boot from embedded SRAM The boot loader is located in system memory. It is used to reprogram the Flash memory by using USART1 (PA9/PA10), USART2 (PA2/PA3), I2C1 (PB6/PB7). 3.
PAGE 15
STM32F334x4 STM32F334x6 STM32F334x8 Functional overview remains in reset mode when the monitored supply voltage is below a specified threshold, VPOR/PDR, without the need for an external reset circuit. • The POR monitors only the VDD supply voltage. During the startup phase it is required that VDDA must arrive first and be greater than or equal to VDD.
PAGE 16
Functional overview 3.5 STM32F334x4 STM32F334x6 STM32F334x8 Interconnect matrix Several peripherals have direct connections between them. This allows autonomous communication between peripherals, saving CPU resources thus power supply consumption. In addition, these hardware connections allow fast and predictable latency. Table 4. STM32F334x4/6/8 peripheral interconnect matrix Interconnect source 16/121 Downloaded from Arrow.com.
PAGE 17
STM32F334x4 STM32F334x6 STM32F334x8 3.6 Functional overview Clocks and startup System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected on reset as default CPU clock. An external 4-32 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled.
PAGE 18
Functional overview STM32F334x4 STM32F334x6 STM32F334x8 Figure 2. Clock tree FLITFCLK to Flash programming interface HSI to I2C1 SYSCLK 8 MHz HSI HSI RC /2 HCLK PLLSRC to cortex System timer /8 SW PLLMUL to AHB bus, core, memory and DMA FHCLK Cortex free HSI x2,x3,.. AHB AHB prescaler prescaler x16 /1,2,..512 /1,2,4,8,16 PLL PLLCLK APB1 running clock PCLK1 to APB1 peripherals HSE SYSCLK If (APB1 prescaler CSS /2,/3,...
PAGE 19
STM32F334x4 STM32F334x6 STM32F334x8 3.7 Functional overview General-purpose inputs/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current capable except for analog inputs.
PAGE 20
Functional overview STM32F334x4 STM32F334x6 STM32F334x8 independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the internal clock period. Up to 51 GPIOs can be connected to the 16 external interrupt lines. 3.10 Fast analog-to-digital converter (ADC) Two 5 MSPS fast analog-to-digital converters, with selectable resolution between 12 and 6 bit, are embedded in the STM32F334x4/6/8 family devices.
PAGE 21
STM32F334x4 STM32F334x6 STM32F334x8 Functional overview input channels. The precise voltage of VREFINT is individually measured for each part by ST during production test and stored in the system memory area. It is accessible in read-only mode. 3.10.3 VBAT battery voltage monitoring This embedded hardware feature allows the application to measure the VBAT battery voltage using the internal ADC channel ADC1_IN17.
PAGE 22
Functional overview 3.13 STM32F334x4 STM32F334x6 STM32F334x8 Ultra-fast comparators (COMP) The STM32F334x4/6/8 devices embed three ultra-fast rail-to-rail comparators (COMP2/4/6) that offer the features below: • Programmable internal or external reference voltage • Selectable output polarity. The reference voltage can be one of the following: • External I/O • DAC output • Internal reference voltage or submultiple (1/4, 1/2, 3/4).
PAGE 23
STM32F334x4 STM32F334x6 STM32F334x8 3.14.1 Functional overview 217 ps high-resolution timer (HRTIM1) The high-resolution timer (HRTIM1) allows generating digital signals with high-accuracy timings, such as PWM or phase-shifted pulses. It consists of 6 timers, 1 master and 5 slaves, totaling 10 high-resolution outputs, which can be coupled by pairs for deadtime insertion.
PAGE 24
Functional overview 3.14.3 STM32F334x4 STM32F334x6 STM32F334x8 General-purpose timers (TIM2, TIM3, TIM15, TIM16 and TIM17) There are up to three general-purpose timers embedded in the STM32F334x4/6/8 (see Table 5 for differences) that can be synchronized. Each general-purpose timer can be used to generate PWM outputs, or act as a simple time base.
PAGE 25
STM32F334x4 STM32F334x6 STM32F334x8 3.14.7 Functional overview SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features: 3.15 • A 24-bit down counter • Auto reload capability • Maskable system interrupt generation when the counter reaches 0.
PAGE 26
Functional overview STM32F334x4 STM32F334x6 STM32F334x8 3.16 Communication interfaces 3.16.1 Inter-integrated circuit interface (I2C) The devices feature an I2C bus interface that can operate in multimaster and slave mode. It can support standard (up to 100 kHz), fast (up to 400 kHz) and fast mode + (up to 1 MHz) modes. It supports 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (2 addresses, 1 with configurable mask). It also includes programmable analog and digital noise filters.
PAGE 27
STM32F334x4 STM32F334x6 STM32F334x8 3.16.2 Functional overview Universal synchronous / asynchronous receivers / transmitters (USARTs) The STM32F334x4/6/8 devices have three embedded universal synchronous receivers/transmitters (USART1, USART2 and USART3). The USART interfaces are able to communicate at speeds of up to 9 Mbits/s. USART1 provides hardware management of the CTS and RTS signals.
PAGE 28
Functional overview STM32F334x4 STM32F334x6 STM32F334x8 Table 9. STM32F334x4/6/8 SPI implementation (continued) SPI features(1) SPI1 NSS pulse mode X TI mode X 1. X = supported. 3.16.4 Controller area network (CAN) The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers.
PAGE 29
STM32F334x4 STM32F334x6 STM32F334x8 Functional overview variation introduced by the finger (or any conductive object) is measured using a proven implementation based on a surface charge transfer acquisition principle. It consists of charging the electrode capacitance and then transferring a part of the accumulated charges into a sampling capacitor, until the voltage across this capacitor has reached a specific threshold.
PAGE 30
Functional overview STM32F334x4 STM32F334x6 STM32F334x8 3.19 Development support 3.19.1 Serial-wire JTAG debug port (SWJ-DP) The Arm SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. 30/121 Downloaded from Arrow.com.
PAGE 31
STM32F334x4 STM32F334x6 STM32F334x8 4 Pinout and pin descriptions Pinout and pin descriptions PA15 PB3 PB4 PB5 PB6 PB7 BOOT0 VSS Figure 4. LQFP32 pinout 32 31 30 29 28 27 26 25 VDD 1 24 PF0/OSC_IN 2 23 PA13 PF1/OSC_OUT 3 22 PA12 PA14 NRST 4 21 PA11 VDDA/VREF+ 5 20 PA10 PA0 6 19 PA9 PA1 7 18 PA8 PA2 8 17 VDD VSS PB1 PA7 PB0 PA4 PA6 10 11 12 13 14 15 16 PA5 9 PA3 LQFP32 MS31949V3 1. The above figure shows the package top view.
PAGE 32
Pinout and pin descriptions STM32F334x4 STM32F334x6 STM32F334x8 PA14 PA15 PC10 PC11 PC12 PD2 PB3 PB4 PB5 PB6 PB7 BOOT0 PB8 VSS PB9 VDD Figure 6.
PAGE 33
STM32F334x4 STM32F334x6 STM32F334x8 Pinout and pin descriptions Figure 7. WLCSP49 ballout 5 6 7 1 2 3 4 A PA14 PA15 PB3 PB6 B VSS VDD PB4 PB5 PB7 C PA11 PA13 PA12 PA10 PC3 D PA8 PA9 PB15 PC7 PA2 PA0 NRST E PB14 PB13 PC5 PA6 PA3 VDDA VSSA VREF- F PB12 PB2 PB0 PA7 PA4 VSS VREF+ G PB11 PB10 PB1 PC4 PA5 VDD PA1 BOOT0 PB9 VDD PB8 VSS PF1 OSC_OUT PF0 OSC_IN MSv44311V1 1. The above figure shows the package top view.
PAGE 34
Pinout and pin descriptions STM32F334x4 STM32F334x6 STM32F334x8 Table 12. Legend/abbreviations used in the pinout table Name Abbreviation Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name Pin name Pin type I/O structure S Supply pin I Input only pin I/O Input / output pin FT 5 V tolerant I/O FTf 5 V tolerant I/O, FM+ capable TTa 3.3 V tolerant I/O directly connected to ADC TT 3.
PAGE 35
STM32F334x4 STM32F334x6 STM32F334x8 Pinout and pin descriptions Table 13.
PAGE 36
Pinout and pin descriptions STM32F334x4 STM32F334x6 STM32F334x8 12 16 22 E4 Pin name (function after reset) PA6(3) Pin type WLCSP49 LQFP64 LQFP48 LQFP32 Pin number I/O I/O structure Table 13.
PAGE 37
STM32F334x4 STM32F334x6 STM32F334x8 Pinout and pin descriptions - 27 35 E1 Pin name (function after reset) PB14 Pin type WLCSP49 LQFP64 LQFP48 LQFP32 Pin number I/O I/O structure Table 13.
PAGE 38
Pinout and pin descriptions STM32F334x4 STM32F334x6 STM32F334x8 Pin name (function after reset) Pin type WLCSP49 LQFP64 LQFP48 LQFP32 Pin number I/O structure Table 13.
PAGE 39
STM32F334x4 STM32F334x6 STM32F334x8 Pinout and pin descriptions 28 29 41 42 57 58 B4 A4 Pin name (function after reset) PB5 PB6 Pin type WLCSP49 LQFP64 LQFP48 LQFP32 Pin number I/O I/O I/O structure Table 13.
PAGE 40
/121 Downloaded from Arrow.com.
PAGE 41
Downloaded from Arrow.com.
PAGE 42
Memory mapping 5 STM32F334x4 STM32F334x6 STM32F334x8 Memory mapping Figure 8.
PAGE 43
STM32F334x4 STM32F334x6 STM32F334x8 - Memory mapping Table 15.
PAGE 44
Memory mapping STM32F334x4 STM32F334x6 STM32F334x8 Table 15. STM32F334x4/6/8 peripheral register boundary addresses (continued) Bus APB1 44/121 Downloaded from Arrow.com.
PAGE 45
STM32F334x4 STM32F334x6 STM32F334x8 6 Electrical characteristics 6.1 Parameter conditions Electrical characteristics Unless otherwise specified, all voltages are referenced to VSS. 6.1.
PAGE 46
Electrical characteristics 6.1.6 STM32F334x4 STM32F334x6 STM32F334x8 Power-supply scheme Figure 11. Power-supply scheme VBAT GPIOs IN VDD 4 x VDD VDDA Level shifter OUT 4 x 100nF + 1 x 4.7 μF Backup circuitry (LSE, RTC, Wake-up logic Backup registers) Power switch 1.65 - 3.6V I/O Logic Kernel logic (CPU, Digital & Memories) Regulator 4xV SS VDDA 10 nF + 1 μF V REF+ VREF- ADC/ DAC Anolog: RCs, PLL, comparators, OPAMP, ... VSSA MS31954V1 Caution: 46/121 Downloaded from Arrow.com.
PAGE 47
STM32F334x4 STM32F334x6 STM32F334x8 6.1.7 Electrical characteristics Measurement of the current consumption Figure 12. Scheme of the current-consumption measurement I DD_VBAT VBAT IDD VDD IDDA VDDA MS19213V1 DocID025409 Rev 8 47/121 101 Downloaded from Arrow.com.
PAGE 48
Electrical characteristics 6.2 STM32F334x4 STM32F334x6 STM32F334x8 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 16: Voltage characteristics, Table 17: Current characteristics, and Table 18: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect the device reliability. Table 16.
PAGE 49
STM32F334x4 STM32F334x6 STM32F334x8 Electrical characteristics Table 17. Current characteristics Symbol Ratings Max.
PAGE 50
Electrical characteristics STM32F334x4 STM32F334x6 STM32F334x8 6.3 Operating conditions 6.3.1 General operating conditions Table 19. General operating conditions Symbol Parameter Conditions Min. Max. Unit fHCLK Internal AHB clock frequency - 0 72 fPCLK1 Internal APB1 clock frequency - 0 36 fPCLK2 Internal APB2 clock frequency - 0 72 Standard operating voltage - 2 3.6 Core, SRAM and Flash memory power supply - 1.65 1.95 2 3.6 2.4 3.6 1.65 3.6 TC I/O –0.3 VDD+0.
PAGE 51
STM32F334x4 STM32F334x6 STM32F334x8 6.3.2 Electrical characteristics Operating conditions at power-up / power-down The parameters given in Table 20 are derived from tests performed under the ambient temperature condition summarized in Table 19. Table 20. Operating conditions at power-up / power-down Symbol Parameter VDD rise time rate tVDD - VDD fall time rate VDDA rise time rate tVDDA 6.3.3 Conditions Max. Unit 0 ∞ ∞ ∞ ∞ µs/V 20 0 - VDDA fall time rate Min.
PAGE 52
Electrical characteristics STM32F334x4 STM32F334x6 STM32F334x8 Table 22. Programmable voltage detector characteristics Symbol Parameter VPVD0 PVD threshold 0 VPVD1 PVD threshold 1 VPVD2 PVD threshold 2 VPVD3 PVD threshold 3 Conditions Min.(1) Typ. Max.(1) Rising edge 2.1 2.18 2.26 Falling edge 2 2.08 2.16 Rising edge 2.19 2.28 2.37 Falling edge 2.09 2.18 2.27 Rising edge 2.28 2.38 2.48 Falling edge 2.18 2.28 2.38 Rising edge 2.38 2.48 2.58 Falling edge 2.28 2.
PAGE 53
STM32F334x4 STM32F334x6 STM32F334x8 Electrical characteristics Table 24. Internal reference voltage calibration values Calibration value name VREFINT_CAL 6.3.5 Description Raw data acquired at temperature of 30 °C VDDA= 3.
PAGE 54
Electrical characteristics STM32F334x4 STM32F334x6 STM32F334x8 Table 25. Typical and maximum current consumption from VDD supply at VDD = 3.
PAGE 55
STM32F334x4 STM32F334x6 STM32F334x8 Electrical characteristics Table 26. Typical and maximum current consumption from the VDDA supply VDDA = 2.4 V Symbol Parameter IDDA Supply current in Run/Sleep mode, code executing from Flash or RAM Conditions (1) HSE bypass HSI clock fHCLK Typ. Max. @ 25 °C VDDA = 3.6 V TA(2) 85 °C 105 °C Typ. Max.
PAGE 56
Electrical characteristics STM32F334x4 STM32F334x6 STM32F334x8 Table 28. Typical and maximum VDDA consumption in Stop and Standby modes Symbo Parameter l Supply current in Standby mode Conditions VDDA supervisor ON Supply current in Stop mode Supply current in Standby mode VDDA supervisor OFF IDDA Supply current in Stop mode Max.(1) Typ. @VDD (VDD = VDDA) TA = TA = TA = 2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V 25 °C 85 °C 105 °C Regulator in run/low-power mode, all oscillators OFF 1.67 1.79 1.
PAGE 57
STM32F334x4 STM32F334x6 STM32F334x8 Electrical characteristics Figure 13. Typical VBAT current consumption (LSE and RTC ON/LSEDRV[1:0] = ’00’) 1.40 1.20 1.65 V 1.00 I VBAT (μA) 1.8 V 0.80 2V 2.4 V 0.60 2.7 V 0.40 3V 0.20 3.3 V 3.6 V 0.00 25°C 60°C 85°C 105°C TA (°C) MS34525V1 Typical current consumption The MCU is placed under the following conditions: • VDD = VDDA = 3.
PAGE 58
Electrical characteristics STM32F334x4 STM32F334x6 STM32F334x8 Table 30. Typical current consumption in Run mode, code with data processing running from Flash memory Typ. Symbol IDD Parameter Conditions Supply current in Run mode from VDD supply Running from HSE crystal clock 8 MHz, code executing from Flash memory IDDA(1) (2) Supply current in Run mode from VDDA supply fHCLK Peripherals enabled Peripherals disabled 72 MHz 70.6 25.2 64 MHz 60.3 22.6 48 MHz 46.0 17.3 32 MHz 31.3 12.
PAGE 59
STM32F334x4 STM32F334x6 STM32F334x8 Electrical characteristics Table 31. Typical current consumption in Sleep mode, code running from Flash or RAM Typ. Symbol IDD Parameter Conditions Supply current in Sleep mode from VDD supply Running from HSE crystal clock 8 MHz, code executing from Flash or RAM IDDA(1) (2) Supply current in Sleep mode from VDDA supply fHCLK Peripherals enabled Peripherals disabled 72 MHz 51.8 6.3 64 MHz 46.4 5.7 48 MHz 35.0 4.40 32 MHz 23.7 3.13 24 MHz 18.0 2.
PAGE 60
Electrical characteristics STM32F334x4 STM32F334x6 STM32F334x8 For the output pins, any external pull-down or external load must also be considered to estimate the current consumption. Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value.
PAGE 61
STM32F334x4 STM32F334x6 STM32F334x8 Electrical characteristics The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. Table 32. Switching output I/O current consumption Symbol Parameter Conditions(1) VDD = 3.3 V Cext = 0 pF C = CINT + CEXT+ CS VDD = 3.3 V Cext = 10 pF C = CINT + CEXT +CS ISW I/O current consumption VDD = 3.3 V Cext = 22 pF C = CINT + CEXT +CS VDD = 3.3 V Cext = 33 pF C = CINT + CEXT+ CS VDD = 3.
PAGE 62
Electrical characteristics STM32F334x4 STM32F334x6 STM32F334x8 On-chip peripheral current consumption The MCU is placed under the following conditions: • All I/O pins are in analog input configuration • All peripherals are disabled unless otherwise mentioned • The given value is calculated by measuring the current consumption: • – With all peripherals clocked off – With only one peripheral clocked on Ambient operating temperature at 25°C and VDD = VDDA = 3.3 V Table 33.
PAGE 63
STM32F334x4 STM32F334x6 STM32F334x8 Electrical characteristics Table 33. Peripheral current consumption (continued) Typical consumption(1) Peripheral Unit IDD I2C1 13.3 - CAN 31.3 - PWR 4.7 - DAC 15.4 - DAC2 8.6 - SPI1 8.2 - 1. The power consumption of the analog part (IDDA) of peripherals such as ADC, DAC, Comparators, OpAmp and others, is not included. Refer to the tables of characteristics in the subsequent sections. 2.
PAGE 64
Electrical characteristics 6.3.6 STM32F334x4 STM32F334x6 STM32F334x8 Wakeup time from low-power mode The wakeup times given in Table 34 are measured starting from the wakeup event trigger up to the first instruction executed by the CPU: • For Stop or Sleep mode: the wakeup event is WFE. • WKUP1 (PA0) pin is used to wake up from Standby, Stop and Sleep modes. All timings are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 19. Table 34.
PAGE 65
STM32F334x4 STM32F334x6 STM32F334x8 Electrical characteristics Table 36. High-speed external user clock characteristics Symbol Parameter Conditions fHSE_ext User external clock source frequency(1) VHSEH OSC_IN input pin high-level voltage VHSEL OSC_IN input pin low-level voltage tw(HSEH) tw(HSEL) tr(HSE) tf(HSE) Min. Typ. Max. Unit 1 8 32 MHz 0.7VDD - VDD VSS - 0.3VDD 15 - - - OSC_IN high or low time(1) V ns OSC_IN rise or fall time (1) - - 20 1.
PAGE 66
Electrical characteristics STM32F334x4 STM32F334x6 STM32F334x8 Figure 15. Low-speed external clock source AC timing diagram tw(LSEH) VLSEH 90% VLSEL 10% tr(LSE) t tf(LSE) tw(LSEL) TLSE MS19215V2 High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 32 MHz crystal/ceramic resonator oscillator.
PAGE 67
STM32F334x4 STM32F334x6 STM32F334x8 Electrical characteristics For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 16). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2.
PAGE 68
Electrical characteristics STM32F334x4 STM32F334x6 STM32F334x8 Table 39. LSE oscillator characteristics (fLSE = 32.768 kHz) (continued) Symbol gm Conditions(1) Min.(2) Typ. Max.
PAGE 69
STM32F334x4 STM32F334x6 STM32F334x8 Electrical characteristics High-speed internal (HSI) RC oscillator Table 40. HSI oscillator characteristics(1) Symbol Parameter fHSI Conditions Min. Typ. - - Frequency TRIM HSI user trimming step DuCy(HSI) Duty cycle Accuracy of the HSI oscillator (factory calibrated) ACCHSI - - - (2) 45 Max. Unit 8 - MHz - (2) - 55 (2) TA = –40 to 105 °C (3) –2.8 - 3.8 TA = –10 to 85 °C –1.9(3) - 2.3(3) TA = 0 to 85 °C -1.
PAGE 70
Electrical characteristics STM32F334x4 STM32F334x6 STM32F334x8 Low-speed internal (LSI) RC oscillator Table 41. LSI oscillator characteristics(1) Symbol fLSI Parameter Min. Typ. Max. Unit 30 40 50 kHz Frequency tsu(LSI)(2) LSI oscillator startup time - - 85 µs IDD(LSI)(2) LSI oscillator power consumption - 0.75 1.2 µA 1. VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified. 2. Guaranteed by design, not tested in production. 6.3.
PAGE 71
STM32F334x4 STM32F334x6 STM32F334x8 6.3.10 Electrical characteristics Memory characteristics Flash memory The characteristics are given at TA = –40 to 105 °C unless otherwise specified. Table 43. Flash memory characteristics Min. Typ. Max.(1) Unit 16-bit programming time TA = –40 to +105 °C 40 53.
PAGE 72
Electrical characteristics STM32F334x4 STM32F334x6 STM32F334x8 Table 45. EMS characteristics Symbol Parameter Level/ Class Conditions VFESD VDD = 3.3 V, LQFP64, TA = +25°C, Voltage limits to be applied on any I/O pin to fHCLK = 72 MHz induce a functional disturbance conforms to IEC 61000-4-2 2B VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD = 3.
PAGE 73
STM32F334x4 STM32F334x6 STM32F334x8 6.3.12 Electrical characteristics Electrical sensitivity characteristics Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination.
PAGE 74
Electrical characteristics STM32F334x4 STM32F334x6 STM32F334x8 The failure is indicated by an out of range parameter: ADC error above a certain limit (higher than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of –5 µA/+0 µA range), or other functional failure (for example reset occurrence or oscillator frequency deviation). The test results are given in Table 49: I/O current injection susceptibility. Table 49.
PAGE 75
STM32F334x4 STM32F334x6 STM32F334x8 Electrical characteristics Table 50. I/O static characteristics (continued) Symbol Parameter Conditions TT, TC and TTa I/O Schmitt trigger hysteresis Vhys Typ. - FT and FTf I/O Input leakage current (3) Ilkg Min. - Max. 200 (1) - 100 (1) - (1) - BOOT0 - 300 TC, FT, TT, FTf and TTa I/O in digital mode VSS ≤VIN ≤VDD - - ±0.1 TTa I/O in digital mode VDD ≤VIN ≤VDDA - - 1 TTa I/O in analog mode VSS ≤VIN ≤VDDA - - ±0.
PAGE 76
Electrical characteristics STM32F334x4 STM32F334x6 STM32F334x8 Figure 20. TC and TTa I/O input characteristics - TTL port VIL/VIH (V) 98 +0.3 lations 5V DD u 0.44 ign sim = V IHmin on des d Base TTL standard requirements V IHmin = 2V VIHmin 2.0 s 0.07 ulation V DD+ im = 0.3 esign s d d on Base V ILmax 1.3 Area not determined VILmax 0.8 0.7 TTL standard requirements V ILmax = 0.8V VDD (V) 2.0 2.7 3.0 3.6 3.3 MS30256V2 Figure 21.
PAGE 77
STM32F334x4 STM32F334x6 STM32F334x8 Electrical characteristics Output driving current The GPIOs (general-purpose input/output) can sink or source up to +/-8 mA, and sink or source up to +/- 20 mA (with a relaxed VOL/VOH). In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 6.
PAGE 78
Electrical characteristics STM32F334x4 STM32F334x6 STM32F334x8 Table 52. I/O AC characteristics(1) OSPEEDRy [1:0] value(1) x0 01 Symbol Parameter fmax(IO)out Maximum frequency(2) tf(IO)out Output high to low level fall time tr(IO)out Output low to high level rise time fmax(IO)out Maximum frequency(2) tf(IO)out Output high to low level fall time tr(IO)out Output low to high level rise time Conditions CL = 50 pF, VDD = 2 V to 3.
PAGE 79
STM32F334x4 STM32F334x6 STM32F334x8 Electrical characteristics Figure 23. I/O AC characteristics definition 90% 10% 50% 50% 90% 10% EXTERNAL OUTPUT ON CL tr(IO)out tf(IO)out T Maximum frequency is achieved if (tr + tf) ≤ (2/3)T and if the duty cycle is (45-55%) when loaded by CL specified in the table “ I/O AC characteristics”. ai14131d 6.3.15 NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 50).
PAGE 80
Electrical characteristics STM32F334x4 STM32F334x6 STM32F334x8 Figure 24. Recommended NRST pin protection ([WHUQDO UHVHW FLUFXLW 9'' 538 1567 ,QWHUQDO UHVHW )LOWHU ) 06 9 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 53. Otherwise the reset is not be taken into account by the device. 3.
PAGE 81
STM32F334x4 STM32F334x6 STM32F334x8 Electrical characteristics Table 55. HRTIM output response to fault protection(1) Symbol Parameter Conditions tLAT(DF) Digital fault response latency tW(FLT) Minimum Fault pulse width tLAT(AF) Analog fault response latency Min. Typ. Max.(2) - 12 25 12.5 - - - 25 43 Propagation delay from HRTIM1_FLTx digital input to HRTIM_CHxy output pin Propagation delay from comparator COMPx_INP input pin to HRTIM_CHxy output pin Unit ns 1.
PAGE 82
Electrical characteristics STM32F334x4 STM32F334x6 STM32F334x8 Table 57. HRTIM output response to external events 1 to 10 (Synchronous mode (1)) (continued) Symbol tLAT(AEEV) tW(FLT) Parameter Min. Typ. Max.(2) Conditions Analog external event response latency Propagation delay from COMPx_INP input pin to HRTIM_CHxy output pin (30pF load) (4) Minimum external event pulse width - Unit - 81 94 ns 12.
PAGE 83
STM32F334x4 STM32F334x6 STM32F334x8 6.3.17 Electrical characteristics Timer characteristics The parameters given in Table 59 are guaranteed by design. Refer to Section 6.3.14: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 59. TIMx(1)(2) characteristics Symbol tres(TIM) fEXT ResTIM tCOUNTER Parameter Timer resolution time Conditions Min. Max.
PAGE 84
Electrical characteristics STM32F334x4 STM32F334x6 STM32F334x8 Table 60. IWDG min./max. timeout period at 40 kHz (LSI) (1) Prescaler divider PR[2:0] bits Min. timeout (ms) RL[11:0] = 0x000 Max. timeout (ms) RL[11:0] = 0xFFF /4 0 0.1 409.6 /8 1 0.2 819.2 /16 2 0.4 1638.4 /32 3 0.8 3276.8 /64 4 1.6 6553.6 /128 5 3.2 13107.2 /256 7 6.4 26214.4 1. These timings are given for a 40 kHz clock but the microcontroller’s internal RC frequency can vary from 30 to 60 kHz.
PAGE 85
STM32F334x4 STM32F334x6 STM32F334x8 Electrical characteristics Table 62. I2C analog filter characteristics(1) Symbol Parameter Min. Max. Unit tAF Maximum pulse width of spikes that are suppressed by the analog filter. 50(2) 260(3) ns 1. Guaranteed by design, not tested in production. 2. Spikes with width below tAF(min.) are filtered. 3. Spikes with width above tAF(max.) are not filtered.
PAGE 86
Electrical characteristics STM32F334x4 STM32F334x6 STM32F334x8 Figure 25. SPI timing diagram - slave mode and CPHA = 0 Figure 26. SPI timing diagram - slave mode and CPHA = 1(1) NSS input SCK input tSU(NSS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 tw(SCKH) tw(SCKL) th(SO) tv(SO) ta(SO) MISO OUTPUT MSB OUT BIT6 OUT tr(SCK) tf(SCK) tdis(SO) LSB OUT th(SI) tsu(SI) MOSI INPUT th(NSS) tc(SCK) MSB IN BIT 1 IN LSB IN ai14135b 1. Measurement points are done at 0.5VDD and with external CL = 30 pF.
PAGE 87
STM32F334x4 STM32F334x6 STM32F334x8 Electrical characteristics Figure 27. SPI timing diagram - master mode(1) High NSS input SCK Output SCK Output tc(SCK) CPHA= 0 CPOL=0 CPHA=1 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=1 tsu(MI) MISO INP UT tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) BIT6 IN MSB IN LSB IN th(MI) MOSI OUTPUT B I T1 OUT MSB OUT tv(MO) LSB OUT th(MO) ai14136c 1. Measurement points are done at 0.5VDD and with external CL = 30 pF. CAN (controller area network) interface Refer to Section 6.3.
PAGE 88
Electrical characteristics STM32F334x4 STM32F334x6 STM32F334x8 Table 64. ADC characteristics (continued) Symbol fADC fS(1) Parameter ADC clock frequency Sampling rate fTRIG(1) External trigger frequency Conditions Min. Typ. Max. Unit - 0.14 - 72 MHz Resolution = 12 bits, Fast Channel 0.01 - 5.14 Resolution = 10 bits, Fast Channel 0.012 - 6 Resolution = 8 bits, Fast Channel 0.014 - 7.2 Resolution = 6 bits, Fast Channel 0.0175 - 9 fADC = 72 MHz Resolution = 12 bits - - 5.
PAGE 89
STM32F334x4 STM32F334x6 STM32F334x8 Electrical characteristics Table 64. ADC characteristics (continued) Symbol tCONV(1) Parameter Total conversion time (including sampling time) Common Mode Input signal CMIR Conditions Min. Typ. Max. Unit fADC = 72 MHz Resolution = 12 bits 0.19 - 8.52 µs 14 to 614 (tS for sampling + 12.5 for successive approximation) Resolution = 12 bits (VSSA+VREF+)/ (VSSA + 2-0.18 VREF+)/2 ADC differential mode 1/fADC (VSSA + VREF+)/2 + 0.18 V 1.
PAGE 90
Electrical characteristics STM32F334x4 STM32F334x6 STM32F334x8 Table 65. Maximum ADC RAIN(1) (continued) Resolution 10 bits 8 bits 6 bits RAIN max. (kΩ) Sampling cycle @ 72 MHz Sampling time [ns] @ 72 MHz Fast channels(2) Slow channels Other channels(3) 1.5 20.83 0.082 NA NA 2.5 34.72 0.270 0.082 0.100 4.5 62.50 0.560 0.390 0.330 7.5 104.17 1.20 0.82 0.68 19.5 270.83 3.30 2.70 2.20 61.5 854.17 10.0 8.2 6.8 181.5 2520.83 33.0 27.0 22.0 601.5 8354.17 100.0 82.
PAGE 91
STM32F334x4 STM32F334x6 STM32F334x8 Electrical characteristics Table 66. ADC accuracy - limited test conditions(1)(2) Symbol Parameter ET EO Total unadjusted error Offset error ±4 ±4.5 Slow channel 4.8 Ms - ±5.5 ±6 Fast channel 5.1 Ms - ±3.5 ±4 Slow channel 4.8 Ms - ±3.5 ±4 Fast channel 5.1 Ms - ±2 ±2 Slow channel 4.8 Ms - ±1.5 ±2 Fast channel 5.1 Ms - ±1.5 ±2 Slow channel 4.8 Ms - ±1.5 ±2 Fast channel 5.1 Ms - ±3 ±4 Slow channel 4.8 Ms - ±5 ±5.5 Fast channel 5.
PAGE 92
Electrical characteristics STM32F334x4 STM32F334x6 STM32F334x8 Table 66. ADC accuracy - limited test conditions(1)(2) (continued) Symbol Parameter SNR(4) THD(4) Signal-tonoise ratio Total harmonic distortion Min. Conditions Typ. Max.(3) Unit (3) Fast channel 5.1 Ms 66 67 - Slow channel 4.8 Ms 66 67 - Fast channel 5.1 Ms ADC clock freq. ≤ 72 MHz Differential Slow channel 4.8 Ms Sampling freq. ≤ 5 Msps VDDA = 3.3 V Fast channel 5.1 Ms Single 25°C ended Slow channel 4.
PAGE 93
STM32F334x4 STM32F334x6 STM32F334x8 Electrical characteristics Table 67. ADC accuracy (1)(2)(3) (continued) Symbol Parameter EL ENOB (5) SINAD (5) SNR(5) THD(5) Single ended Integral linearity error Effective number of bits Differential ADC clock freq. ≤ 72 MHz, Sampling freq. ≤ 5 Msps 2.0 V ≤ VDDA ≤ 3.6 V Single ended Differential Single ended Signal-tonoise and distortion ratio Differential Single ended Signal-tonoise ratio Total harmonic distortion Min.(4) Max.(4) Fast channel 5.
PAGE 94
Electrical characteristics STM32F334x4 STM32F334x6 STM32F334x8 Table 68. ADC accuracy(1)(2) at 1MSPS Symbol Parameter Typ. Max(3) Fast channel ±2.5 ±5 Slow channel ±3.5 ±5 Fast channel ±1 ±2.5 ±1.5 ±2.5 ±2 ±3 Test conditions ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error Slow channel ADC Freq. ≤ 72 MHz Fast channel Sampling Freq. ≤ 1MSPS 2.4 V ≤ VDDA = VREF+ ≤ 3.
PAGE 95
STM32F334x4 STM32F334x6 STM32F334x8 Electrical characteristics Figure 30. Typical connection diagram using the ADC VDD Sample and hold ADC converter VT 0.6 V RAIN (1) VAIN RADC AINx VT 0.6 V Cparasitic 12-bit converter IL ± 1 μA CADC MS19881V3 1. Refer to Table 64 for the values of RAIN. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high Cparasitic value downgrades conversion accuracy.
PAGE 96
Electrical characteristics STM32F334x4 STM32F334x6 STM32F334x8 Table 69. DAC characteristics (continued) Symbol Min. Typ. Max. Unit Given for a 10-bit input code DAC1 channel 1 - - ±0.5 LSB Given for a 12-bit input code DAC1 channel 1 - - ±2 LSB Given for a 10-bit input code DAC1 channel 2 & DAC2 channel 1 - - -0.75/+0.
PAGE 97
STM32F334x4 STM32F334x6 STM32F334x8 Electrical characteristics Figure 31. 12-bit buffered /non-buffered DAC Buffered/Non-buffered DAC Buffer(1) R L DAC_OUTx 12-bit digital to analog converter C L ai17157V3 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. 6.3.
PAGE 98
Electrical characteristics STM32F334x4 STM32F334x6 STM32F334x8 Figure 32. Maximum VREFINT scaler startup time from power-down 6.3.22 Operational amplifier characteristics Table 71. Operational amplifier characteristics(1) Symbol Parameter Condition Min. Typ. Max. Unit VDDA Analog supply voltage - 2.4 - 3.6 V CMIR Common mode input range - 0 - VDDA V - - 4 - - 6 25°C, No Load on output. - - 1.6 All voltage/Temp.
PAGE 99
STM32F334x4 STM32F334x6 STM32F334x8 Electrical characteristics Table 71. Operational amplifier characteristics(1) (continued) Symbol VOHSAT VOLSAT ϕm tOFFTRIM tWAKEUP Parameter Condition High saturation voltage(2) Low saturation voltage Min. Typ. Rload = min, Input at VDDA. VDDA-100 - Rload = 20K, Input at VDDA. VDDA-20 - Rnetwork PGA gain error Ibias PGA BW Unit mV Rload = min, input at 0 V - - 100 Rload = 20K, input at 0 V.
PAGE 100
Electrical characteristics STM32F334x4 STM32F334x6 STM32F334x8 Table 71. Operational amplifier characteristics(1) (continued) Symbol en Parameter Voltage noise density Condition Min. Typ. Max. @ 1KHz, Output loaded with 4 KΩ - 109 - @ 10KHz, Output loaded with 4 KΩ - 43 1. Guaranteed by design, not tested in production. 2. The saturation voltage can also be limited by the Iload. 3. R2 is the internal resistance between OPAMP output and OPAMP inverting input.
PAGE 101
STM32F334x4 STM32F334x6 STM32F334x8 6.3.23 Electrical characteristics Temperature sensor (TS) characteristics Table 72. Temperature sensor (TS) characteristics Symbol Parameter TL(1) Min. Typ. Max. Unit - ±1 ±2 °C Average slope 4.0 4.3 4.6 mV/°C Voltage at 25 °C 1.34 1.43 1.52 V 4 - 10 µs 2.2 - - µs VSENSE linearity with temperature (1) Avg_Slope V25 tSTART(1) TS_temp(1)(2) Startup time ADC sampling time when reading the temperature 1.
PAGE 102
Package information STM32F334x4 STM32F334x6 STM32F334x8 7 Package information 7.1 Package mechanical data To meet the environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 102/121 Downloaded from Arrow.com.
PAGE 103
STM32F334x4 STM32F334x6 STM32F334x8 7.2 Package information LQFP32 package information LQFP32 is a 32-pin, 7 x 7mm low-profile quad flat package. Figure 34. LQFP32 package outline c A1 A A2 SEATING PLANE C 0.25 mm ccc GAUGE PLANE C K D A1 L D1 L1 D3 24 17 16 32 9 PIN 1 IDENTIFICATION 1 E E1 E3 b 25 8 e 5V_ME_V2 1. Drawing is not to scale. Table 75. LQFP32 mechanical data Inches(1) Millimeters Symbol Min. Typ. Max. Min. Typ. Max. A - - 1.600 - - 0.0630 A1 0.
PAGE 104
Package information STM32F334x4 STM32F334x6 STM32F334x8 Table 75. LQFP32 mechanical data (continued) Inches(1) Millimeters Symbol Min. Typ. Max. Min. Typ. Max. b 0.300 0.370 0.450 0.0118 0.0146 0.0177 c 0.090 - 0.200 0.0035 - 0.0079 D 8.800 9.000 9.200 0.3465 0.3543 0.3622 D1 6.800 7.000 7.200 0.2677 0.2756 0.2835 D3 - 5.600 - - 0.2205 - E 8.800 9.000 9.200 0.3465 0.3543 0.3622 E1 6.800 7.000 7.200 0.2677 0.2756 0.2835 E3 - 5.600 - - 0.
PAGE 105
STM32F334x4 STM32F334x6 STM32F334x8 Package information Device marking for LQFP32 The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 36. LQFP32 marking example (package top view) (1) Product Identification STM32F 334K6T6 Y WW Revision code R Pin 1 indentifier MSv33098V1 1.
PAGE 106
Package information 7.3 STM32F334x4 STM32F334x6 STM32F334x8 LQFP48 package information LQFP48 is a 48-pin, 7 x 7mm low-profile quad flat package. Figure 37. LQFP48 package outline c A1 A A2 SEATING PLANE C 0.25 mm GAUGE PLANE ccc C K A1 D L D1 L1 D3 36 25 37 24 48 PIN 1 IDENTIFICATION E E1 E3 b 13 1 12 e 5B_ME_V2 1. Drawing is not to scale. Table 76. LQFP48 package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.
PAGE 107
STM32F334x4 STM32F334x6 STM32F334x8 Package information Table 76. LQFP48 package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max E 8.800 9.000 9.200 0.3465 0.3543 0.3622 E1 6.800 7.000 7.200 0.2677 0.2756 0.2835 E3 - 5.500 - - 0.2165 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - 0.0394 - k 0° 3.5° 7° 0° 3.5° 7° ccc - - 0.080 - - 0.0031 1.
PAGE 108
Package information STM32F334x4 STM32F334x6 STM32F334x8 Device marking for LQFP48 The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 39. LQFP48 marking example (package top view) (1) Product Identification STM32F 334C6T6 Y WW Revision code R Pin 1 indentifier MSv33099V1 1.
PAGE 109
STM32F334x4 STM32F334x6 STM32F334x8 7.4 Package information LQFP64 package information LQFP64 is a 64-pin, 10 x 10 mm low-profile quad flat package. Figure 40. LQFP64 package outline 0.25 mm GAUGE PLANE c A1 A A2 SEATING PLANE C A1 ccc C D D1 D3 K L L1 33 48 32 49 64 E E1 E3 b 17 PIN 1 IDENTIFICATION 16 1 e 5W_ME_V3 1. Drawing is not to scale. Table 77. LQFP64 package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.
PAGE 110
Package information STM32F334x4 STM32F334x6 STM32F334x8 Table 77. LQFP64 package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max θ 0° 3.5° 7° 0° 3.5° 7° L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - Number of pins N 64 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 41. Recommended footprint for the LQFP64 package 48 33 0.3 0.5 49 32 12.7 10.3 10.3 17 64 1.2 16 1 7.8 12.
PAGE 111
STM32F334x4 STM32F334x6 STM32F334x8 Package information Device marking for LQFP64 The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 42. LQFP64 marking example (package top view) Revision code R (1) Engineering Sample marking STM32F334 R6T6 Pin 1 indentifier Y WW MSv33100V1 1.
PAGE 112
Package information 7.5 STM32F334x4 STM32F334x6 STM32F334x8 WLCSP49 package information Figure 43. WLCSP - 49 ball, 3.89x3.74 mm, 0.5 mm pitch, wafer level chip scale, package outline bbb Z A1 BALL LOCATION e1 F G 7 A1 1 A DETAIL A E e2 E e G aaa e A TOP VIEW BOTTOM VIEW A3 A2 D D SIDE VIEW A2 BUMP FRONT VIEW A2 SEATING PLANE DETAIL A ROTATED 90 B01F_WLCSP49_ME_V1 1. Dimension is measured at the maximum bump diameter parallel to primary datum Z. 2.
PAGE 113
STM32F334x4 STM32F334x6 STM32F334x8 Package information Table 78. WLCSP - 49 ball, 3.89x3.74 mm, 0.5 mm pitch, wafer level chip scale, mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 0.62 - - 0.0244 A1 - 0.23 - - 0.009 - A2 - 0.36 - - 0.014 - A3 - 0.025(2) - - 0.001 - b 0.30 0.33 0.36 0.012 0.013 0.014 D 3.87 3.89 3.91 0.152 0.153 0.154 E 3.72 3.74 3.76 0.146 0.147 0.148 e - 0.50 - - 0.020 - e1 - 3.00 - - 0.
PAGE 114
Package information STM32F334x4 STM32F334x6 STM32F334x8 Table 79. WLCSP - 49 ball, 3.89x3.74 mm, 0.5 mm pitch, wafer level chip scale, recommended PCB design rules Dimension 114/121 Downloaded from Arrow.com. Recommended values Pitch 0.5 mm Dpad 0.290 mm Dsm 0.350 mm typ. (depends on the soldermask registration tolerance) Stencil opening 0.310 mm Stencil thickness 0.
PAGE 115
STM32F334x4 STM32F334x6 STM32F334x8 Package information Device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 45. WLCSP49 marking example (package top view) 1.
PAGE 116
Package information 7.6 STM32F334x4 STM32F334x6 STM32F334x8 Thermal characteristics The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max x ΘJA) Where: • TA max is the maximum ambient temperature in ° C, • ΘJA is the package junction-to-ambient thermal resistance, in ° C/W, • PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/O max), • PINT max is the product of IDD and VDD, expressed in Watts.
PAGE 117
STM32F334x4 STM32F334x6 STM32F334x8 Package information Example: high-performance application Assuming the following application conditions: Maximum ambient temperature TAmax = 82 °C (measured according to JESD51-2), IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output mode at low level with IOL = 20 mA, VOL= 1.3 V PINTmax = 50 mA × 3.5 V = 175 mW PIOmax = 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.
PAGE 118
Ordering information 8 STM32F334x4 STM32F334x6 STM32F334x8 Ordering information Table 81. Ordering information scheme Example: STM32 F Device family STM32 = Arm®-based 32-bit microcontroller Product type F = general-purpose Device subfamily 334 = STM32F334xx, 2.0 to 3.
PAGE 119
STM32F334x4 STM32F334x6 STM32F334x8 9 Revision history Revision history Table 82. Document revision history Date Revision 19-Jun-2014 1 Initial release.
PAGE 120
Revision history STM32F334x4 STM32F334x6 STM32F334x8 Table 82. Document revision history (continued) Date 120/121 Downloaded from Arrow.com. Revision Changes 23-Nov--2017 7 Updated: – Footnotes of Table 25: Typical and maximum current consumption from VDD supply at VDD = 3.
PAGE 121
STM32F334x4 STM32F334x6 STM32F334x8 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.