Datasheet

Electrical characteristics STM32F303x6/x8
84/121 DocID025083 Rev 7
6.3.17 Communication interfaces
I
2
C interface characteristics
The I
2
C interface meets the timings requirements of the I
2
C-bus specification and user
manual rev. 03 for:
• Standard-mode (Sm): with a bit rate up to 100 Kbit/s
• Fast-mode (Fm): with a bit rate up to 400 Kbit/s
• Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
The I
2
C timings requirements are guaranteed by design when the I
2
C peripheral is properly
configured (refer to Reference manual).
The SDA and SCL I/O requirements are met with the following restrictions: the SDA and
SCL I/O pins are not "true" open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and VDD is disabled, but is still present. Only FTf I/O pins
support Fm+ low-level output current maximum requirement. Refer to
Section 6.3.14: I/O
port characteristics for the I
2
C I/O characteristics.
All I
2
C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog
filter characteristics:
Table 57. IWDG min./max. timeout period at 40 kHz (LSI)
(1)
1. These timings are given for a 40 kHz clock but the microcontroller’s internal RC frequency can vary from 30
to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the phasing
of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty.
Prescaler divider PR[2:0] bits
Min. timeout (ms)
RL[11:0] = 0x000
Max. timeout (ms)
RL[11:0] = 0xFFF
/4 0 0.1 409.6
/8 1 0.2 819.2
/16 2 0.4 1638.4
/32 3 0.8 3276.8
/64 4 1.6 6553.6
/128 5 3.2 13107.2
/256 7 6.4 26214.4
Table 58. WWDG min./max. timeout value at 72 MHz (PCLK)
(1)
1. Guaranteed by design, not tested in production.
Prescaler WDGTB Min. timeout value Max. timeout value
1 0 0.05687 3.6409
2 1 0.1137 7.2817
4 2 0.2275 14.564
8 3 0.4551 29.127
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