Datasheet

DocID025083 Rev 7 77/121
STM32F303x6/x8 Electrical characteristics
101
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in
Figure 19 and Figure 20 for standard I/Os.
Figure 19. TC and TTa I/O input characteristics - CMOS port
I
lkg
Input leakage
current
(3)
TC, FT, TT, FTf and TTa
I/O in digital mode
V
SS
≤ V
IN
≤ V
DD
--±0.1
µA
TTa I/O in digital mode
V
DD
≤ V
IN
≤ V
DDA
--1
TTa I/O in analog mode
V
SS
≤ V
IN
≤ V
DDA
--±0.2
FT and FTf I/O
(4)
V
DD
≤ V
IN
≤ 5 V
--10
R
PU
Weak pull-up
equivalent resistor
(5)
V
IN
= V
SS
25 40 55 kΩ
R
PD
Weak pull-down
equivalent resistor
(5)
V
IN
= V
DD
25 40 55 kΩ
C
IO
I/O pin capacitance - - 5 - pF
1. Data based on design simulation.
2. Tested in production.
3. Leakage could be higher than the maximum value. If negative current is injected on adjacent pins. Refer to Table 51: I/O
current injection susceptibility.
4. To sustain a voltage higher than V
DD
+0.3 V, the internal pull-up/pull-down resistors must be disabled.
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimum (~10% order).
Table 52. I/O static characteristics (continued)
Symbol Parameter Conditions Min. Typ. Max. Unit
069
9
''
9
9
,+PLQ

9
,/PD[

9
,/
9
,+
9

 
9
,/PD[
9
''


  
&026VWDQGDUGUHTXLUHPHQWV9,/PD[ 9
''
9
,+PLQ
9
''

$UHDQRWGHWHUPLQHG
7HVWHGLQSURGXFWLRQ
7HVWHGLQSURGXFWLRQ
%DVHGRQGHVLJQVLPXODWLRQV
%DVHGRQGHVLJQVLPXODWLRQV
&026VWDQGDUGUHTXLUHPHQWV9
,+
PLQ 9
''
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