Datasheet

Functional overview STM32F303x6/x8
16/121 DocID025083 Rev 7
Standby mode, SRAM and register contents are lost except for registers in the Backup
domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a
rising edge on the WKUP pin, or an RTC alarm occurs.
Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop
or Standby mode.
3.5 Interconnect matrix
Several peripherals have direct connections between them. This allows autonomous
communication between peripherals, saving CPU resources thus power supply
consumption. In addition, these hardware connections allow fast and predictable latency.
Note: For more details about the interconnect actions, refer to the corresponding sections in the
RM0364 reference manual.
Table 4. STM32F303x6/8 peripheral interconnect matrix
Interconnect source
Interconnect
destination
Interconnect action
TIMx
TIMx Timers synchronization or chaining
ADCx
DACx
Conversion triggers
DMA Memory to memory transfer trigger
COMPx Comparator output blanking
COMPx TIMx Timer input: ocrefclear input, input capture
ADCx TIM1 Timer triggered by analog watchdog
GPIO
RTCCLK
HSE/32
MC0
TIM16
Clock source used as input channel for HSI and
LSI calibration
CSS
CPU (hard fault)
RAM (parity error)
COMPx
PVD
GPIO
TIM1
TIM15, 16, 17
Timer break
GPIO
TIMx External trigger, timer break
ADCx
DACx
Conversion external trigger
DACx COMPx Comparator inverting input
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