Datasheet

DS9118 Rev 14 93/149
STM32F303xB STM32F303xC Electrical characteristics
125
Figure 24. Recommended NRST pin protection
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the V
IL(NRST)
max level specified in
Table 57. Otherwise the reset will not be taken into account by the device.
6.3.16 Timer characteristics
The parameters given in Table 58 are guaranteed by design.
Refer to Section 6.3.14: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
MS19878V1
External
reset circuitry
(1)
NRST
(2)
0.1 μF
V
DD
R
PU
Filter
Internal reset
Table 58. TIMx
(1)(2)
characteristics
1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3, TIM4, TIM8, TIM15, TIM16 and TIM17
timers.
2. Guaranteed by design.
Symbol Parameter Conditions Min Max Unit
t
res(TIM)
Timer resolution time
-1-
t
TIMxCLK
f
TIMxCLK
= 72 MHz 13.9 - ns
f
TIMxCLK
= 144 MHz
x=1.8
6.95 - ns
f
EXT
Timer external clock
frequency on CH1 to CH4
-0
f
TIMxCLK
/2
MHz
f
TIMxCLK
= 72 MHz 0 36 MHz
Res
TIM
Timer resolution
TIMx (except TIM2) - 16
bit
TIM2 - 32
t
COUNTER
16-bit counter clock period
- 1 65536
t
TIMxCLK
f
TIMxCLK
= 72 MHz 0.0139 910 µs
f
TIMxCLK
= 144 MHz
x=1.8
0.0069 455 µs
t
MAX_COUNT
Maximum possible count
with 32-bit counter
- - 65536 × 65536
t
TIMxCLK
f
TIMxCLK
= 72 MHz - 59.65 s
f
TIMxCLK
= 144 MHz
x=1.8
- 29.825 s
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