Datasheet

Electrical characteristics STM32F303xB STM32F303xC
118/149 DS9118 Rev 14
6.3.19 DAC electrical specifications
Table 75. DAC characteristics
Symbol Parameter Conditions Min Typ Max Unit
V
DDA
Analog supply voltage - 2.4 - 3.6 V
R
LOAD
(1)
Resistive load
DAC output
buffer ON
Connected to V
SSA
5- -
kΩ
Connected to V
DDA
25 - -
R
O
(1)
Output impedance DAC output buffer OFF - - 15 kΩ
C
LOAD
(1)
Capacitive load DAC output buffer ON - - 50 pF
V
DAC_OUT
(1)
Voltage on DAC_OUT
output
Corresponds to 12-bit input
code (0x0E0) to (0xF1C) at
V
DDA
= 3.6 V
and (0x155) and (0xEAB) at
V
DDA
= 2.4 V DAC output buffer
ON.
0.2 - V
DDA
– 0.2 V
DAC output buffer OFF - 0.5 V
DDA
- 1LSB mV
I
DDA
(3)
DAC DC current
consumption in quiescent
mode (Standby mode)
(2)
With no load, middle code
(0x800) on the input.
-- 380µA
With no load, worst code
(0xF1C) on the input.
-- 480µA
DNL
(3)
Differential non linearity
Difference between two
consecutive code-1LSB)
Given for a 10-bit input code - - ±0.5 LSB
Given for a 12-bit input code - - ±2 LSB
INL
(3)
Integral non linearity
(difference between
measured value at Code i
and the value at Code i on a
line drawn between Code 0
and last Code 4095)
Given for a 10-bit input code - - ±1 LSB
Given for a 12-bit input code - - ±4 LSB
Offset
(3)
Offset error (difference
between measured value at
Code (0x800) and the ideal
value = V
DDA
/2)
---±10mV
Given for a 10-bit input code at
V
DDA
= 3.6 V
-- ±3LSB
Given for a 12-bit input code at
V
DDA
= 3.6 V
-- ±12LSB
Gain error
(3)
Gain error Given for a 12-bit input code - - ±0.5 %
t
SETTLING
(3)
Settling time (full scale: for a
12-bit input code transition
between the lowest and the
highest input codes when
DAC_OUT reaches final
value ±1LSB
C
LOAD
≤ 50 pF,
R
LOAD
≥ 5 kΩ
-3 4 µs
Update
rate
(3)
Max frequency for a correct
DAC_OUT change when
small variation in the input
code (from code i to i+1LSB)
C
LOAD
≤ 50 pF,
R
LOAD
≥ 5 kΩ
-- 1MS/s
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