Datasheet

DS9118 Rev 14 117/149
STM32F303xB STM32F303xC Electrical characteristics
125
Figure 34. ADC accuracy characteristics
Figure 35. Typical connection diagram using the ADC
1. Refer to Table 68 for the values of R
AIN
.
2. C
parasitic
represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7
pF). A high C
parasitic
value will downgrade conversion accuracy. To remedy
this, f
ADC
should be reduced.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 11. The 10 nF capacitor
should be ceramic (good quality) and it should be placed as close as possible to the chip.
(1) Example of an actu al transfer curve
(2) The ideal transfer cu rve
(3) End point correlation line
4095
4094
4093
5
4
3
2
1
0
7
6
12 3 456 7
4093 4094 4095 4096
(1)
(2)
(3)
ai14395e
ET = Total unadjusted Error: maximum deviation
between the actual and the ideal transfer curves.
E
O = Offset Error: deviation between the first actual
transition and the last actual one.
E
G = Gain Error: deviation between the last ideal
transition and the last actual one.
E
D = Differential Linearity Error: maximum deviation
between actual steps and the ideal one.
E
L = Integral Linearity Error: maximum deviation
between any actual transition and the end-point
correlation line.
V
SSA
VDDA
1 LSB IDEAL
ED
EL
EO
ET
EG
[1LSB IDEAL =
VREF+
4096
V
DDA
4096
(or depending on package)
12-bit
converter
Sample and hold ADC
converter
R
AIN
(1)
AINx
V
AIN
C parasitic
V DD
V T
0.6 V
V
T
0.6 V
I
L ± 1 μA
R
ADC
C ADC
MS19881V3
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