Datasheet

ManualsBrandsST ManualsEmbedded Processors & ControllersMicrocontroller 32bit 128KB LQFP

This is information on a product in full production.

October 2018 DS9118 Rev 14 1/149

STM32F303xB STM32F303xC

Arm

-based Cortex

-M4 32b MCU+FPU, up to 256KB Flash+

48KB SRAM, 4 ADCs, 2 DAC ch., 7 comp, 4 PGA, timers, 2.0-3.6 V

Datasheet - production data

Features

• Core: Arm

Cortex

-M4 32-bit CPU with FPU

(72 MHz max), single-cycle multiplication and

HW division,

90 DMIPS (from CCM), DSP

instruction and MPU (memory protection unit)

• Operating conditions:

–V

, V

DDA

voltage range: 2.0 V to 3.6 V

• Memories

– 128 to 256 Kbytes of Flash memory

– Up to 40 Kbytes of SRAM, with HW parity

check implemented on the first 16 Kbytes.

– Routine booster: 8 Kbytes of SRAM on

instruction and data bus, with HW parity

check (CCM)

• CRC calculation unit

• Reset and supply management

– Power-on/power-down reset (POR/PDR)

– Programmable voltage detector (PVD)

– Low-power modes: Sleep, Stop and

Standby

–V

BAT

supply for RTC and backup registers

• Clock management

–4

to 32 MHz crystal oscillator

– 32 kHz oscillator for RTC with calibration

– Internal 8 MHz RC with x 16 PLL option

–

Internal 40 kHz oscillator

• Up to 87 fast I/Os

– All mappable on external interrupt vectors

– Several 5 V-tolerant

• Interconnect matrix

• 12-channel DMA controller

•

Four ADCs 0.20 µS (up to 39 channels) with

selectable resolution of 12/10/8/6 bits, 0 to

3.6 V conversion range, single

ended/differential input, separate analog

supply from 2 to 3.6 V

•

Two 12-bit DAC channels with analog supply

from 2.4 to 3.6 V

•

Seven fast rail-to-rail analog comparators with

analog supply from 2 to 3.6 V

•

Four operational amplifiers that can be used in

PGA mode, all terminals accessible with

analog supply from 2.4 to 3.6 V

•

Up to 24 capacitive sensing channels supporting

touchkey, linear and rotary touch sensor

• Up to

13 timers

– One 32-bit timer and two 16-bit timers with

up to 4 IC/OC/PWM or pulse counter and

quadrature (incremental) encoder input

–

Two 16-bit 6-channel advanced-control

timer

s, with up to 6 PWM channels,

deadtime generation and emergency stop

– One 16-bit timer with 2 IC/OCs, 1

OCN/PWM, deadtime generation and

emergency stop

– Two 16-bit timers with IC/OC/OCN/PWM,

deadtime generation and emergency stop

– Two watchdog timers (independent,

window)

– SysTick timer: 24-bit downcounter

–

Two 16-bit basic timers to drive the DAC

• Calendar RTC with Alarm, periodic wakeup

from Stop/Standby

• Communication interfaces

– CAN interface (2.0B Active)

–Two I

C Fast mode plus (1 Mbit/s) with

20 mA current sink, SMBus/PMBus,

wakeup from STOP

LQFP64 (10 × 10 mm)

LQFP100 (14 × 14 mm)

LQFP48 (7 × 7 mm)

WLCSP100 (0.4 mm pitch)

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Summary of content (149 pages)

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STM32F303xB STM32F303xC Arm®-based Cortex®-M4 32b MCU+FPU, up to 256KB Flash+ 48KB SRAM, 4 ADCs, 2 DAC ch., 7 comp, 4 PGA, timers, 2.0-3.6 V Datasheet - production data Features • Core: Arm® Cortex®-M4 32-bit CPU with FPU (72 MHz max), single-cycle multiplication and HW division, 90 DMIPS (from CCM), DSP instruction and MPU (memory protection unit) LQFP48 (7 × 7 mm) LQFP64 (10 × 10 mm) LQFP100 (14 × 14 mm) • Operating conditions: – VDD, VDDA voltage range: 2.0 V to 3.
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STM32F303xB STM32F303xC – Up to five USART/UARTs (ISO 7816 interface, LIN, IrDA, modem control) – Up to three SPIs, two with multiplexed half/full duplex I2S interface, 4 to 16 programmable bit frames – USB 2.0 full speed interface – Infrared transmitter • Serial wire debug, Cortex®-M4 with FPU ETM, JTAG • 96-bit unique ID Table 1. Device summary Reference Part number STM32F303xB STM32F303CB, STM32F303RB, STM32F303VB STM32F303xC STM32F303CC, STM32F303RC, STM32F303VC 2/149 Downloaded from Arrow.com.
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STM32F303xB STM32F303xC Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 Arm® Cortex®-M4 core with FPU with embedded Flash and SRAM . . . . 14 3.2 Memory protection unit (MPU) . . . . . . . . . . . .
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Contents STM32F303xB STM32F303xC 3.17.2 General-purpose timers (TIM2, TIM3, TIM4, TIM15, TIM16, TIM17) . . . 24 3.17.3 Basic timers (TIM6, TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.17.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.17.5 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.17.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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STM32F303xB STM32F303xC 7 Contents 6.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.3.6 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.3.8 Internal clock source characteristics . . . . . . . . . .
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List of tables STM32F303xB STM32F303xC List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46.
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STM32F303xB STM32F303xC Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. List of tables EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of figures STM32F303xB STM32F303xC List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42.
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STM32F303xB STM32F303xC Figure 49. Figure 50. List of figures package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 WLCSP100 – 100L, 4.166 x 4.628 mm 0.4 mm pitch wafer level chip scale package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 WLCSP100, 0.4 mm pitch wafer level chip scale package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Introduction 1 STM32F303xB STM32F303xC Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32F303xB/STM32F303xC microcontrollers. This STM32F303xB/STM32F303xC datasheet should be read in conjunction with the STM32F303x, STM32F358xC and STM32F328x4/6/8 reference manual (RM0316). The reference manual is available from the STMicroelectronics website www.st.com.
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STM32F303xB STM32F303xC 2 Description Description The STM32F303xB/STM32F303xC family is based on the high-performance Arm® Cortex®M4 32-bit RISC core with FPU operating at a frequency of up to 72 MHz, and embedding a floating point unit (FPU), a memory protection unit (MPU) and an embedded trace macrocell (ETM).
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Description STM32F303xB STM32F303xC Table 2.
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STM32F303xB STM32F303xC Description Figure 1. STM32F303xB/STM32F303xC block diagram TPIU ETM SWJTAG Trace/Trig OBL Ibus Cortex M4 CPU Flash interface Voltage reg. 3.3 V to 1.8V MPU/FPU Fmax: 72 MHz System NVIC CCM RAM 8KB POR Supply Supervision Reset Int. POR /PDR NRESET VDDA VSSA PVD SRAM 40 KB @VDDA @VDDA GP DMA1 7 channels RC HS 8MHz GP DMA2 5 channels PLL @VDDIO RC LS XTAL OSC 4 -32 MHz Ind. WDG32K Standby interface AHBPCLK Temp.
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Functional overview STM32F303xB STM32F303xC 3 Functional overview 3.1 Arm® Cortex®-M4 core with FPU with embedded Flash and SRAM The Arm Cortex-M4 processor with FPU is the latest generation of Arm processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts.
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STM32F303xB STM32F303xC 3.4 Functional overview Embedded SRAM STM32F303xB/STM32F303xC devices feature up to 48 Kbytes of embedded SRAM with hardware parity check. The memory can be accessed in read/write at CPU clock speed with 0 wait states, allowing the CPU to achieve 90 Dhrystone Mips at 72 MHz (when running code from the CCM (Core Coupled Memory) RAM). • 8 Kbytes of CCM RAM mapped on both instruction and data bus, used to execute critical routines or to access data (parity check on all of CCM RAM).
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Functional overview STM32F303xB STM32F303xC 3.7 Power management 3.7.1 Power supply schemes • VSS, VDD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator. It is provided externally through VDD pins. • VSSA, VDDA = 2.0 to 3.6 V: external analog power supply for ADC, DACs, comparators operational amplifiers, reset blocks, RCs and PLL. The minimum voltage to be applied to VDDA differs from one analog peripheral to another.
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STM32F303xB STM32F303xC 3.7.4 Functional overview Low-power modes The STM32F303xB/STM32F303xC supports three low-power modes to achieve the best compromise between low-power consumption, short startup time and available wakeup sources: • Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. • Stop mode Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers.
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Functional overview STM32F303xB STM32F303xC Table 4.
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STM32F303xB STM32F303xC Functional overview Figure 2. Clock tree FLITFCLK to Flash programming interface HSI to I2Cx (x = 1,2) SYSCLK I2SSRC SYSCLK to I2Sx (x = 2,3) Ext. clock I2S_CKIN USB prescaler /1,1.5 8 MHz HSI HSI RC USBCLK to USB interface /2 HCLK PLLSRC PLLMUL PLL x2,x3,.. x16 SW HSI PLLCLK HSE /8 AHB AHB prescaler /1,2,..512 APB1 prescaler /1,2,4,8,16 SYSCLK OSC_OUT OSC_IN OSC32_IN OSC32_OUT PCLK1 SYSCLK HSI LSE 4-32 MHz HSE OSC APB2 prescaler /1,2,4,8,16 /32 LSE OSC 32.
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Functional overview 3.10 STM32F303xB STM32F303xC General-purpose input/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current capable except for analog inputs.
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STM32F303xB STM32F303xC 3.13 Functional overview Fast analog-to-digital converter (ADC) four fast analog-to-digital converters 5 MSPS, with selectable resolution between 12 and 6 bit, are embedded in the STM32F303xB/STM32F303xC family devices. The ADCs have up to 39 external channels. Some of the external channels are shared between ADC1&2 and between ADC3&4. Channels can be configured to be either single-ended input or differential input. The ADCs can perform conversions in single-shot or scan modes.
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Functional overview 3.13.3 STM32F303xB STM32F303xC VBAT battery voltage monitoring This embedded hardware feature allows the application to measure the VBAT battery voltage using the internal ADC channel ADC1_IN17. As the VBAT voltage may be higher than VDDA, and thus outside the ADC input range, the VBAT pin is internally connected to a bridge divider by 2. As a consequence, the converted digital value is half the VBAT voltage. 3.13.
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STM32F303xB STM32F303xC 3.16 Functional overview Fast comparators (COMP) The STM32F303xB/STM32F303xC devices embed seven fast rail-to-rail comparators with programmable reference voltage (internal or external), hysteresis and speed (low speed for low-power) and with selectable output polarity. The reference voltage can be one of the following: • External I/O • DAC output pin • Internal reference voltage or submultiple (1/4, 1/2, 3/4).
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Functional overview 3.17.1 STM32F303xB STM32F303xC Advanced timers (TIM1, TIM8) The advanced-control timers (TIM1 and TIM8) can each be seen as a three-phase PWM multiplexed on six channels. They have complementary PWM outputs with programmable inserted dead-times. They can also be seen as complete general-purpose timers.
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STM32F303xB STM32F303xC 3.17.4 Functional overview Independent watchdog (IWDG) The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management.
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Functional overview • STM32F303xB STM32F303xC 17-bit Auto-reload counter for periodic interrupt with wakeup from STOP/STANDBY capability. The RTC clock sources can be: 3.19 • A 32.768 kHz external crystal • A resonator or oscillator • The internal low-power RC oscillator (typical frequency of 40 kHz) • The high-speed external clock divided by 32. Inter-integrated circuit interface (I2C) Up to two I2C bus interfaces can operate in multimaster and slave modes.
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STM32F303xB STM32F303xC Functional overview Table 7. STM32F303xB/STM32F303xC I2C implementation (continued) I2C features(1) I2C1 I2C2 SMBus X X Wakeup from STOP X X 1. X = supported. 3.20 Universal synchronous/asynchronous receiver transmitter (USART) The STM32F303xB/STM32F303xC devices have three embedded universal synchronous/asynchronous receiver transmitters (USART1, USART2 and USART3). The USART interfaces are able to communicate at speeds of up to 9 Mbits/s.
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Functional overview 3.22 STM32F303xB STM32F303xC Serial peripheral interface (SPI)/Inter-integrated sound interfaces (I2S) Up to three SPIs are able to communicate up to 18 Mbits/s in slave and master modes in full-duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits.
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STM32F303xB STM32F303xC 3.25 Functional overview Infrared Transmitter The STM32F303xB/STM32F303xC devices provide an infrared transmitter solution. The solution is based on internal connections between TIM16 and TIM17 as shown in the figure below. TIM17 is used to provide the carrier frequency and TIM16 provides the main signal to be sent. The infrared output signal is available on PB9 or PA13.
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Functional overview STM32F303xB STM32F303xC Table 10.
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STM32F303xB STM32F303xC Functional overview 3.27 Development support 3.27.1 Serial wire JTAG debug port (SWJ-DP) The Arm SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. 3.27.
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Pinouts and pin description 4 STM32F303xB STM32F303xC Pinouts and pin description PC14/OSC32_IN 1 2 3 PC15/OSC32_OUT 4 PF0/OSC_IN 5 6 PA14 PB4 PB3 PA15 PB5 PB6 BOOT0 PB7 PB8 VSS VDD VSS PA13 PA12 PA11 PA10 PA9 PA8 PB15 PB14 PB13 PB12 VDD PB11 VSS PA3 PA4 PA2 10 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24 PB10 PA1 28 27 26 9 PB2 PA0 8 PB1 VDDA 30 29 7 PA7 PB0 NRST VSSA/VREF- 33 32 31 LQFP48 PA6 PF1/OSC_OUT 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 PA5 VBAT PC13 P
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STM32F303xB STM32F303xC Pinouts and pin description VDD VSS PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12 VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PB10 PB11 VSS VDD 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 LQFP64 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PA3 PF4 VBAT PC13 PC14/OSC32_IN PC15/OSC32_OUT PF0/OSC_IN PF1/OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA/VREFVDDA PA0 PA1 PA2 BOOT0 PB7 PB6 PB
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Pinouts and pin description STM32F303xB STM32F303xC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 VDD VSS PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 Figure 6.
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STM32F303xB STM32F303xC Pinouts and pin description Figure 7.
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Pinouts and pin description STM32F303xB STM32F303xC Table 12. Legend/abbreviations used in the pinout table Name Abbreviation Pin name Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name Pin type I/O structure S Supply pin I Input only pin I/O Input / output pin FT 5 V tolerant I/O FTf 5 V tolerant I/O, FM+ capable TTa 3.3 V tolerant I/O directly connected to ADC TC Standard 3.
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STM32F303xB STM32F303xC Pinouts and pin description Table 13.
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Pinouts and pin description STM32F303xB STM32F303xC Table 13.
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STM32F303xB STM32F303xC Pinouts and pin description Table 13.
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Pinouts and pin description STM32F303xB STM32F303xC Table 13.
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STM32F303xB STM32F303xC Pinouts and pin description Table 13.
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Pinouts and pin description STM32F303xB STM32F303xC Table 13.
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STM32F303xB STM32F303xC Pinouts and pin description Table 13.
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Pinouts and pin description STM32F303xB STM32F303xC 1. Function availability depends on the chosen device. When using the small packages (48 and 64 pin packages), the GPIO pins which are not present on these packages, must not be configured in analog mode. 2. PC13, PC14 and PC15 are supplied through the power switch.
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/149 Downloaded from Arrow.com. - - TIM8_ CH1 SWDIO TIM16_ -JTMS CH1N - TIM2_ CH1_ ETR SWCLK -JTCK PA13 PA14 PA15 JTDI - TIM16_ CH1 - PA12 AF2 AF1 AF0 Port & Pin Name - - AF4 - I2C1_ SCL TSC_ I2C1_ G4_IO4 SDA TSC_ G4_IO3 - AF3 - TIM1_CH2N AF6 SPI1_ NSS SPI3_NSS, I2S3_WS TIM8_ TIM1_BKIN CH2 IR_ OUT - AF5 AF8 AF9 AF10 USART2_ RX USART2_ TX USART3_ CTS - - - TIM1_ BKIN - - - - TIM4_ CH3 USART1_ COMP2 TIM4_ CAN_TX RTS_DE _OUT CH2 AF7 Table 14.
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/149 Downloaded from Arrow.com. - PB14 RTC_ REFIN - PB13 PB15 AF0 Port & Pin Name - TIM15_ CH1 TIM15_ TIM15_ CH2 CH1N - AF2 - AF1 - TIM1_ CH3N - - TSC_ G6_IO3 TSC_ G6_IO4 AF4 AF3 TIM1_ CH1N AF6 SPI2_MOSI, I2S2_SD - SPI2_MISO, TIM1_ I2S2ext_SD CH2N SPI2_SCK, I2S2_CK AF5 - USART3_ RTS_DE USART3_ CTS AF7 - - - AF8 Table 15.
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/149 Downloaded from Arrow.com. EVENTOUT EVENTOUT EVENTOUT EVENTOUT PF4 PF6 PF9 PF10 - PF1 EVENTOUT - PF0 PF2 AF1 Port & Pin Name - - TIM4_CH4 COMP1_OUT - - - AF2 TIM15_CH2 TIM15_CH1 - - - - - AF3 - - I2C2_SCL - - I2C2_SCL I2C2_SDA AF4 SPI2_SCK SPI2_SCK - - - - - AF5 Table 19.
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STM32F303xB STM32F303xC 5 Memory mapping Memory mapping Figure 8.
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Memory mapping STM32F303xB STM32F303xC Table 20. STM32F303xB/STM32F303xC memory map, peripheral register boundary addresses(1) Bus AHB3 AHB2 AHB1 APB2 54/149 Downloaded from Arrow.com.
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STM32F303xB STM32F303xC Memory mapping Table 20.
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Electrical characteristics STM32F303xB STM32F303xC 6 Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range).
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STM32F303xB STM32F303xC 6.1.6 Electrical characteristics Power supply scheme Figure 11. Power supply scheme VBAT Backup circuitry (LSE, RTC, Wakeup logic, Backup registers) OUT GP I/Os IN Level shifter Power switch 1.65 – 3.6 V VDD I/O logic Kernel logic (CPU, digital & memories) 4 x VDD Regulator 4 x 100 nF + 1 x 4.7 μF 4 x VSS VDDA VDDA VREF+ 10 nF + 1 μF ADC/DAC VREF- Analog: RCs, PLL,comparators, OPAMP, .... VSSA MS19875V5 1.
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Electrical characteristics 6.1.7 STM32F303xB STM32F303xC Current consumption measurement Figure 12. Current consumption measurement scheme I DD_VBAT VBAT IDD VDD IDDA VDDA MS19213V1 6.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 21: Voltage characteristics, Table 22: Current characteristics, and Table 23: Thermal characteristics may cause permanent damage to the device.
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STM32F303xB STM32F303xC Electrical characteristics 2. VREF+ must be always lower or equal than VDDA (VREF+ ≤VDDA). If unused then it must be connected to VDDA. 3. VIN maximum must always be respected. Refer to Table 22: Current characteristics for the maximum allowed injected current values. 4. Include VREF- pin. Table 22. Current characteristics Symbol Ratings Max.
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Electrical characteristics STM32F303xB STM32F303xC 6.3 Operating conditions 6.3.1 General operating conditions Table 24. General operating conditions Symbol Parameter Conditions Min Max fHCLK Internal AHB clock frequency - 0 72 fPCLK1 Internal APB1 clock frequency - 0 36 fPCLK2 Internal APB2 clock frequency - 0 72 Standard operating voltage - 2 3.6 2 3.
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STM32F303xB STM32F303xC 6.3.2 Electrical characteristics Operating conditions at power-up / power-down The parameters given in Table 25 are derived from tests performed under the ambient temperature condition summarized in Table 24. Table 25. Operating conditions at power-up / power-down Symbol Parameter VDD rise time rate tVDD - VDD fall time rate VDDA rise time rate tVDDA 6.3.
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Electrical characteristics STM32F303xB STM32F303xC Table 27. Programmable voltage detector characteristics Symbol Parameter VPVD0 PVD threshold 0 VPVD1 PVD threshold 1 VPVD2 PVD threshold 2 VPVD3 PVD threshold 3 Min(1) Typ Max(1) Rising edge 2.1 2.18 2.26 Falling edge 2 2.08 2.16 Rising edge 2.19 2.28 2.37 Falling edge 2.09 2.18 2.27 Rising edge 2.28 2.38 2.48 Falling edge 2.18 2.28 2.38 Rising edge 2.38 2.48 2.58 Falling edge 2.28 2.38 2.48 Rising edge 2.
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STM32F303xB STM32F303xC 6.3.4 Electrical characteristics Embedded reference voltage The parameters given in Table 28 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 24. Table 28. Embedded internal reference voltage Symbol Parameter VREFINT Internal reference voltage TS_vrefint VRERINT TCoeff Conditions Min Typ Max Unit –40 °C < TA < +105 °C 1.2 1.23 1.25 V (1) –40 °C < TA < +85 °C 1.2 1.
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Electrical characteristics STM32F303xB STM32F303xC The parameters given in Table 30 to Table 34 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 24. Table 30. Typical and maximum current consumption from VDD supply at VDD = 3.
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STM32F303xB STM32F303xC Electrical characteristics Table 30. Typical and maximum current consumption from VDD supply at VDD = 3.6V (continued) All peripherals enabled Symbol Parameter Conditions IDD Supply current in Sleep mode, executing from Flash or RAM External clock (HSE bypass) Internal clock (HSI) fHCLK Max @ TA(1) Typ All peripherals disabled Max @ TA(1) Typ 25 °C 85 °C 105 °C 72 MHz 44.0 48.4 49.4 50.5 64 MHz 39.2 43.3 44.0 48 MHz 29.6 32.7 32 MHz 19.
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Electrical characteristics STM32F303xB STM32F303xC Table 32. Typical and maximum VDD consumption in Stop and Standby modes Symbol Parameter IDD Typ @VDD (VDD=VDDA) Max(1) 2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V TA = TA = TA = 25 °C 85 °C 105 °C Conditions Regulator in run mode, 20.05 20.33 20.42 20.50 20.67 20.80 44.2(2) 350 Supply all oscillators OFF current in Stop mode Regulator in low-power 7.63 7.77 7.90 8.07 8.17 8.33 30.
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STM32F303xB STM32F303xC Electrical characteristics Table 34. Typical and maximum current consumption from VBAT supply Symbol Para meter Max @VBAT = 3.6 V(2) Typ @VBAT Conditions (1) LSE & RTC ON; "Xtal mode" lower driving capability; Backup LSEDRV[1: domain 0] = '00' IDD_VBAT supply LSE & RTC current ON; "Xtal mode" higher driving capability; LSEDRV[1: 0] = '11' 1.65V 1.8V 2V 0.48 0.50 0.52 2.4V 2.7V 0.58 3V Unit TA = TA = TA = 3.3V 3.6V 25°C 85°C 105°C 0.65 0.72 0.80 0.90 1.1 1.5 2.
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Electrical characteristics STM32F303xB STM32F303xC Typical current consumption The MCU is placed under the following conditions: • VDD = VDDA = 3.
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STM32F303xB STM32F303xC Electrical characteristics Table 36. Typical current consumption in Sleep mode, code running from Flash or RAM Typ Symbol IDD Parameter Conditions Supply current in Sleep mode from VDD supply Running from HSE crystal clock 8 MHz, code executing from Flash or RAM IDDA(1) (2) Supply current in Sleep mode from VDDA supply fHCLK Peripherals enabled Peripherals disabled 72 MHz 44.1 7.0 64 MHz 39.7 6.3 48 MHz 30.3 4.9 32 MHz 20.5 3.5 24 MHz 15.4 2.8 16 MHz 10.
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Electrical characteristics STM32F303xB STM32F303xC I/O system current consumption The current consumption of the I/O system has two components: static and dynamic. I/O static current consumption All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 54: I/O static characteristics.
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STM32F303xB STM32F303xC Electrical characteristics Table 37. Switching output I/O current consumption Symbol Parameter Conditions(1) VDD = 3.3 V Cext = 0 pF C = CINT + CEXT+ CS VDD = 3.3 V Cext = 10 pF C = CINT + CEXT +CS ISW I/O current consumption VDD = 3.3 V Cext = 22 pF C = CINT + CEXT +CS VDD = 3.3 V Cext = 33 pF C = CINT + CEXT+ CS VDD = 3.3 V Cext = 47 pF C = CINT + CEXT+ CS I/O toggling frequency (fSW) Typ 2 MHz 0.90 4 MHz 0.93 8 MHz 1.16 18 MHz 1.60 36 MHz 2.51 48 MHz 2.
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Electrical characteristics STM32F303xB STM32F303xC On-chip peripheral current consumption The MCU is placed under the following conditions: • all I/O pins are in analog input configuration • all peripherals are disabled unless otherwise mentioned • the given value is calculated by measuring the current consumption • – with all peripherals clocked off – with only one peripheral clocked on ambient operating temperature at 25°C and VDD = VDDA = 3.3 V. Table 38.
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STM32F303xB STM32F303xC Electrical characteristics Table 38. Peripheral current consumption (continued) Peripheral Typical consumption(1) Unit IDD TIM6 9.7 TIM7 12.1 WWDG 6.4 SPI2 40.4 SPI3 40.0 USART2 41.9 USART3 40.2 UART4 36.5 UART5 30.8 I2C1 10.5 I2C2 10.4 USB 26.2 CAN 33.4 PWR 5.7 DAC 15.4 µA/MHz 1. The power consumption of the analog part (IDDA) of peripherals such as ADC, DAC, Comparators, OpAmp etc. is not included.
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Electrical characteristics 6.3.6 STM32F303xB STM32F303xC Wakeup time from low-power mode The wakeup times given in Table 39 are measured starting from the wakeup event trigger up to the first instruction executed by the CPU: • For Stop or Sleep mode: the wakeup event is WFE. • WKUP1 (PA0) pin is used to wakeup from Standby, Stop and Sleep modes. All timings are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 24. Table 39.
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STM32F303xB STM32F303xC 6.3.7 Electrical characteristics External clock source characteristics High-speed external user clock generated from an external source In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal has to respect the I/O characteristics in Section 6.3.14. However, the recommended clock input waveform is shown in Figure 14. Table 40.
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Electrical characteristics STM32F303xB STM32F303xC Low-speed external user clock generated from an external source In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal has to respect the I/O characteristics in Section 6.3.14. However, the recommended clock input waveform is shown in Figure 15 Table 41.
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STM32F303xB STM32F303xC Electrical characteristics High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 32 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 42.
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Electrical characteristics STM32F303xB STM32F303xC For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 16). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2.
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STM32F303xB STM32F303xC Electrical characteristics Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 43.
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Electrical characteristics STM32F303xB STM32F303xC Figure 17. Typical application with a 32.768 kHz crystal Resonator with integrated capacitors CL1 OSC32_IN fLSE Drive programmable amplifier 32.768 kHz resonator OSC32_OUT CL2 MS30253V2 Note: An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one. 6.3.
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STM32F303xB STM32F303xC Electrical characteristics Figure 18. HSI oscillator accuracy characterization results for soldered parts 4% MAX MIN 3% 2% 1% 0% -40 -20 0 20 40 60 80 100 T [ºC] 120 A -1% -2% -3% -4% MS30985V4 Low-speed internal (LSI) RC oscillator Table 45. LSI oscillator characteristics(1) Symbol fLSI Parameter Frequency Min Typ Max Unit 30 40 50 kHz tsu(LSI)(2) LSI oscillator startup time - - 85 µs IDD(LSI)(2) LSI oscillator power consumption - 0.75 1.2 µA 1.
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Electrical characteristics 6.3.9 STM32F303xB STM32F303xC PLL characteristics The parameters given in Table 46 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 24. Table 46.
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STM32F303xB STM32F303xC 6.3.11 Electrical characteristics EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs.
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Electrical characteristics STM32F303xB STM32F303xC Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values.
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STM32F303xB STM32F303xC Electrical characteristics Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: • A supply overvoltage is applied to each power supply pin • A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78A IC latch-up standard. Table 52. Electrical sensitivities Symbol LU 6.3.
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Electrical characteristics STM32F303xB STM32F303xC Table 53. I/O current injection susceptibility Functional susceptibility Symbol IINJ Note: 86/149 Downloaded from Arrow.com.
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STM32F303xB STM32F303xC 6.3.14 Electrical characteristics I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 54 are derived from tests performed under the conditions summarized in Table 24. All I/Os are CMOS and TTL compliant. Table 54. I/O static characteristics Symbol VIL VIH Parameter Low level input voltage High level input voltage Conditions Min Vhys Ilkg Input leakage current (3) Max Unit (1) TC and TTa I/O - - 0.
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Electrical characteristics STM32F303xB STM32F303xC All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements is shown in Figure 19 and Figure 20 for standard I/Os. Figure 19. TC and TTa I/O input characteristics - CMOS port VIL/VIH (V) equir dard r stan MOS VIHmin 2.0 Tested ts VIH emen C uction in prod 1.3 min = D 0.7VD 98 ns +0.3 5V DD imulatio 0.
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STM32F303xB STM32F303xC Electrical characteristics Figure 21. Five volt tolerant (FT and FTf) I/O input characteristics - CMOS port VIL/VIH (V) min ts VIH emen requir ndard sta MOS 0.2 ulations V DD+ = 0.5 sign sim e on d ased C 2.0 VDD = 0.7 V IHmin B -0.2 lations u 75V DD = 0.4 esign sim on d d e s a V ILmax B Area not determined 1.0 ax = 0.3VDD ments VILm rd require CMOS standa 0.5 VDD (V) 2.0 3.6 2.7 MS30257V3 Figure 22.
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Electrical characteristics STM32F303xB STM32F303xC Output driving current The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or source up to +/- 20 mA (with a relaxed VOL/VOH). In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 6.
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STM32F303xB STM32F303xC Electrical characteristics Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 23 and Table 56, respectively. Unless otherwise specified, the parameters given are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 24. Table 56.
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Electrical characteristics STM32F303xB STM32F303xC Figure 23. I/O AC characteristics definition 90% 10% 50% 50% 90% 10% EXTERNAL OUTPUT ON 50pF tr(IO)out tf(IO)out T Maximum frequency is achieved if (tr + tf) ≤ 2/3)T and if the duty cycle is (45-55%) when loaded by 50pF ai14131c 6.3.15 NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 54).
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STM32F303xB STM32F303xC Electrical characteristics Figure 24. Recommended NRST pin protection VDD External reset circuitry (1) RPU Internal reset NRST (2) Filter 0.1 μF MS19878V1 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 57. Otherwise the reset will not be taken into account by the device. 6.3.
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Electrical characteristics STM32F303xB STM32F303xC Table 59. IWDG min/max timeout period at 40 kHz (LSI) (1) Prescaler divider PR[2:0] bits Min timeout (ms) RL[11:0]= 0x000 Max timeout (ms) RL[11:0]= 0xFFF /4 0 0.1 409.6 /8 1 0.2 819.2 /16 2 0.4 1638.4 /32 3 0.8 3276.8 /64 4 1.6 6553.6 /128 5 3.2 13107.2 /256 7 6.4 26214.4 1. These timings are given for a 40 kHz clock but the microcontroller’s internal RC frequency can vary from 30 to 60 kHz.
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STM32F303xB STM32F303xC 6.3.17 Electrical characteristics Communications interfaces I2C interface characteristics The I2C interface meets the timings requirements of the I2C-bus specification and user manual rev.
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Electrical characteristics STM32F303xB STM32F303xC 1. The I2C characteristics are the requirements from I2C bus specification rev03. They are guaranteed by design when I2Cx_TIMING register is correctly programmed (Refer to the RM0316 reference manual). 2. The maximum tHD;DAT could be 3.45 µs, 0.9 µs and 0.45 µs for standard mode, fast mode and fast mode plus, but must be less than the maximum of tVD;DAT or tVD;ACK by a transition time. 3.
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STM32F303xB STM32F303xC Electrical characteristics SPI/I2S characteristics Unless otherwise specified, the parameters given in Table 63 for SPI or in Table 64 for I2S are derived from tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 24. Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S). Table 63.
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Electrical characteristics STM32F303xB STM32F303xC Figure 26. SPI timing diagram - slave mode and CPHA = 0 Figure 27. SPI timing diagram - slave mode and CPHA = 1(1) NSS input SCK input tSU(NSS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 tw(SCKH) tw(SCKL) th(SO) tv(SO) ta(SO) MISO OUTPUT MSB OUT BIT6 OUT tr(SCK) tf(SCK) tdis(SO) LSB OUT th(SI) tsu(SI) MOSI INPUT th(NSS) tc(SCK) MSB IN BIT 1 IN LSB IN ai14135b 1. Measurement points are done at 0.5VDD and with external CL = 30 pF.
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STM32F303xB STM32F303xC Electrical characteristics Figure 28. SPI timing diagram - master mode(1) High NSS input SCK Output CPHA= 0 CPOL=0 SCK Output tc(SCK) CPHA=1 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=1 tsu(MI) MISO INP UT tw(SCKH) tw(SCKL) MSB IN tr(SCK) tf(SCK) BIT6 IN LSB IN th(MI) MOSI OUTPUT MSB OUT tv(MO) B I T1 OUT LSB OUT th(MO) ai14136c 1. Measurement points are done at 0.5VDD and with external CL = 30 pF. DS9118 Rev 14 99/149 125 Downloaded from Arrow.com.
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Electrical characteristics STM32F303xB STM32F303xC Table 64. I2S characteristics(1) Symbol Parameter Conditions Min Max fCK 1/tc(CK) I2S clock frequency Master data: 16 bits, audio freq=48 kHz 1.496 1.503 Slave 0 12.
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STM32F303xB STM32F303xC Electrical characteristics Figure 29. I2S slave timing diagram (Philips protocol)(1) 1. Measurement points are done at 0.5VDD and with external CL=30 pF. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 30. I2S master timing diagram (Philips protocol)(1) 1. Measurement points are done at 0.5VDD and with external CL=30 pF. 2. LSB transmit/receive of the previously transmitted byte.
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Electrical characteristics STM32F303xB STM32F303xC USB characteristics Table 65. USB startup time Symbol tSTARTUP(1) Parameter USB transceiver startup time Max Unit 1 µs 1. Guaranteed by design. Table 66. USB DC electrical characteristics Symbol Conditions Min.(1) Max.(1) Unit - 3.0(3) 3.6 V I(USB_DP, USB_DM) 0.2 - Parameter Input levels USB operating voltage(2) VDD VDI(4) Differential input sensitivity VCM(4) Differential common mode range Includes VDI range 0.8 2.
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STM32F303xB STM32F303xC Electrical characteristics Table 67. USB: Full-speed electrical characteristics(1) Symbol Parameter Conditions Min Typ Max Unit CL = 50 pF 4 - 20 ns CL = 50 pF 4 - 20 ns tr/tf 90 - 110 % - 1.3 - 2.0 V driving high and low 28 40 44 Ω Driver characteristics tr tf trfm VCRS Rise time(2) Fall time (2) Rise/ fall time matching Output signal crossover voltage Output driver Z Impedance(3) DRV 1. Guaranteed by design. 2.
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/149 Downloaded from Arrow.com. Common Mode Input signal Range CMIR(1) ADC differential mode Resolution = 12 bits - - - - Typ 8.52 10 601.5 8.35 Max (VSSA+VREF+)/2 -10% (VSSA+VREF+)/2 (VSSA+VREF+)/2 + 10% 14 to 614 (tS for sampling + 12.5 for successive approximation) 0.19 fADC = 72 MHz Resolution = 12 bits 1.5 - 0.021 fADC = 72 MHz - Min Conditions V 1/fADC µs µs 1/fADC µs Unit 2.
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STM32F303xB STM32F303xC Electrical characteristics Figure 32. ADC typical current consumption on VDDA pin 1000 ADC current consumption (μA) 900 800 700 Single-ended mode 600 Differential mode 500 400 300 200 100 0 5 1 0.2 Clock frequency (MSPS) MS36607V1 Figure 33. ADC typical current consumption on VREF+ pin 200 ADC current consumption (μA) 180 Single-ended mode 160 Differential mode 140 120 100 80 60 40 20 0 5 1 0.
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Electrical characteristics STM32F303xB STM32F303xC Table 69. Maximum ADC RAIN (1) Resolution 12 bits 10 bits 8 bits 6 bits RAIN max (kΩ) Sampling cycle @ 72 MHz Sampling time [ns] @ 72 MHz Fast channels(2) Slow channels Other channels(3) 1.5 20.83 0.018 NA NA 2.5 34.72 0.150 NA 0.022 4.5 62.50 0.470 0.220 0.180 7.5 104.17 0.820 0.560 0.470 19.5 270.83 2.70 1.80 1.50 61.5 854.17 8.20 6.80 4.70 181.5 2520.83 22.0 18.0 15.0 601.5 8354.17 82.0 68.0 47.0 1.
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STM32F303xB STM32F303xC Electrical characteristics 3. Channels available on PA2, PA6, PB1, PB12. Table 70. ADC accuracy - limited test conditions, 100-pin packages (1)(2) Symbol Parameter ET Total unadjusted error Single ended Differential Single ended EO Offset error Differential Single ended EG Gain error Differential ED EL Differential linearity error Integral linearity error Effective ENOB(4) number of bits Signal-tonoise and (4) SINAD distortion ratio Min Conditions ADC clock freq.
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Electrical characteristics STM32F303xB STM32F303xC Table 70. ADC accuracy - limited test conditions, 100-pin packages (1)(2) (continued) Symbol Parameter Single ended SNR(4) THD(4) Signal-tonoise ratio Total harmonic distortion Min Conditions ADC clock freq. ≤ 72 MHz Sampling freq ≤ 5 Msps VDDA = VREF+ = 3.3 V 25°C 100-pin package Differential Single ended Differential Max (3) Typ Fast channel 5.1 Ms 66 67 - Slow channel 4.8 Ms 66 67 - Fast channel 5.1 Ms 69 70 - Slow channel 4.
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STM32F303xB STM32F303xC Electrical characteristics Table 71. ADC accuracy, 100-pin packages(1)(2)(3) Symbol Parameter ET Single Ended Total unadjusted error Differential Single Ended EO Offset error Differential Single Ended EG ED EL ENOB (5) Gain error Differential linearity error Integral linearity error Effective number of bits Min (4) Max(4) Fast channel 5.1 Ms - ±6.5 Slow channel 4.8 Ms - ±6.5 Fast channel 5.1 Ms - ±4 Slow channel 4.8 Ms - ±4 Fast channel 5.
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Electrical characteristics STM32F303xB STM32F303xC Table 71. ADC accuracy, 100-pin packages(1)(2)(3) (continued) Symbol Parameter Single Ended Signal-toSINAD noise and (5) distortion ratio SNR(5) Signal-tonoise ratio Min (4) Max(4) Fast channel 5.1 Ms 64 - Slow channel 4.8 Ms 63 - Fast channel 5.1 Ms 67 - Slow channel 4.8 Ms 67 - Fast channel 5.1 Ms 64 - Slow channel 4.8 Ms 64 - Fast channel 5.1 Ms 67 - Slow channel 4.8 Ms 67 - Fast channel 5.1 Ms - -74 Slow channel 4.
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STM32F303xB STM32F303xC Electrical characteristics Table 72. ADC accuracy - limited test conditions, 64-pin packages(1)(2) Symbol Parameter ET Single ended Total unadjusted error Differential Single ended EO Offset error Differential Single ended EG Gain error Differential ED EL ENOB (4) SINAD (4) Differential linearity error Integral linearity error Effective number of bits Signal-tonoise and distortion ratio Min Conditions ADC clock freq. ≤ 72 MHz Sampling freq. ≤ 5 Msps VDDA = 3.
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Electrical characteristics STM32F303xB STM32F303xC Table 72. ADC accuracy - limited test conditions, 64-pin packages(1)(2) (continued) Symbol Parameter Single ended SNR(4) THD(4) Signal-tonoise ratio Total harmonic distortion Min Conditions ADC clock freq. ≤ 72 MHz Sampling freq ≤ 5 Msps VDDA = 3.3 V 25°C 64-pin package Differential Single ended Differential Max (3) Typ Fast channel 5.1 Ms 66 67 - Slow channel 4.8 Ms 66 67 - Fast channel 5.1 Ms 69 70 - Slow channel 4.
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STM32F303xB STM32F303xC Electrical characteristics Table 73. ADC accuracy, 64-pin packages(1)(2)(3) Symbol Parameter ET Single ended Total unadjusted error Differential Single ended EO Offset error Differential Single ended EG Gain error Differential ED EL ENOB (5) SINAD (5) Differential linearity error Integral linearity error Effective number of bits Signal-tonoise and distortion ratio Min(4) Max Fast channel 5.1 Ms - ±6.5 Slow channel 4.8 Ms - ±6.5 Fast channel 5.
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Electrical characteristics STM32F303xB STM32F303xC Table 73. ADC accuracy, 64-pin packages(1)(2)(3) (continued) Symbol Parameter Single ended SNR(5) THD(5) Signal-tonoise ratio Total harmonic distortion Min(4) Max Fast channel 5.1 Ms 64 - Slow channel 4.8 Ms 64 - Fast channel 5.1 Ms 67 - Slow channel 4.8 Ms 67 - Fast channel 5.1 Ms - -75 Slow channel 4.8 Ms - -75 Fast channel 5.1 Ms - -79 Slow channel 4.8 Ms - -78 Conditions ADC clock freq.
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STM32F303xB STM32F303xC Electrical characteristics Figure 34. ADC accuracy characteristics [1LSB IDEAL = VDDA VREF+ (or 4096 4096 depending on package) EG 4095 4094 (1) Example of an actu al transfe r curve (2) The ideal transfer cu rve (3) End point correlation line 4093 ET = Total unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO = Offset Error: deviation between the first actual transition and the last actual one.
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Electrical characteristics 6.3.19 STM32F303xB STM32F303xC DAC electrical specifications Table 75. DAC characteristics Symbol VDDA RLOAD(1) RO(1) CLOAD (1) VDAC_OUT (1) IDDA(3) Parameter Conditions Min Typ Max Unit - 2.4 - 3.6 V Resistive load DAC output Connected to VSSA buffer ON Connected to V DDA 5 - - 25 - - Output impedance DAC output buffer OFF - - 15 kΩ Capacitive load DAC output buffer ON - - 50 pF 0.2 - VDDA – 0.2 V DAC output buffer OFF - 0.
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STM32F303xB STM32F303xC Electrical characteristics Table 75. DAC characteristics (continued) Symbol Parameter Conditions Wakeup time from off state tWAKEUP(3) (Setting the ENx bit in the DAC Control register) CLOAD ≤50 pF, RLOAD ≥ 5 kΩ Power supply rejection ratio C LOAD = 50 pF, PSRR+ (1) (to VDDA) (static DC No RLOAD ≥ 5 kΩ, measurement Min Typ Max Unit - 6.5 10 µs - –67 –40 dB 1. Guaranteed by design. 2.
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Electrical characteristics 6.3.20 STM32F303xB STM32F303xC Comparator characteristics Table 76. Comparator characteristics(1) Symbol Conditions Min Typ Max Analog supply voltage - 2 - 3.6 VIN Comparator input voltage range - 0 - VDDA VBG Scaler input voltage - - 1.2 - VSC Scaler offset voltage - - ±5 ±10 mV tS_SC VREFINT scaler startup time from power down First VREFINT scaler activation after device power on - - 1(2) s Next activations - - 0.
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STM32F303xB STM32F303xC Electrical characteristics Table 76.
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Electrical characteristics 6.3.21 STM32F303xB STM32F303xC Operational amplifier characteristics Table 77. Operational amplifier characteristics(1) Symbol Parameter Condition Min Typ Max Unit VDDA Analog supply voltage - 2.4 - 3.6 V CMIR Common mode input range - 0 - VDDA V 25°C, No Load on output. - - 4 All voltage/Temp. - - 6 25°C, No Load on output. - - 1.6 All voltage/Temp.
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STM32F303xB STM32F303xC Electrical characteristics Table 77. Operational amplifier characteristics(1) (continued) Symbol PGA gain Rnetwork Parameter Condition Min Typ Max Unit - 2 - - - 4 - - - 8 - - - 16 - - Gain=2 - 5.4/5.4 - R2/R1 internal resistance values in Gain=4 PGA mode (3) Gain=8 - 16.2/5.4 - - 37.8/5.4 - - 40.5/2.7 - Non inverting gain value - Gain=16 PGA gain error Ibias PGA BW en PGA gain error - -1% - 1% OPAMP input bias current - - - ±0.
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Electrical characteristics STM32F303xB STM32F303xC Figure 38. OPAMP voltage noise versus frequency 6.3.22 Temperature sensor characteristics Table 78. TS characteristics Symbol TL(1) Avg_Slope(1) V25 tSTART(1) TS_temp(1)(2) Parameter Min Typ Max Unit - ±1 ±2 °C Average slope 4.0 4.3 4.6 mV/°C Voltage at 25 °C 1.34 1.43 1.52 V 4 - 10 µs 2.2 - - µs VSENSE linearity with temperature Startup time ADC sampling time when reading the temperature 1. Guaranteed by design. 2.
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STM32F303xB STM32F303xC 6.3.23 Electrical characteristics VBAT monitoring characteristics Table 80. VBAT monitoring characteristics Symbol Parameter Min Typ Max Unit KΩ R Resistor bridge for VBAT - 50 - Q Ratio on VBAT measurement - 2 - Error on Q -1 - +1 % ADC sampling time when reading the VBAT 1mV accuracy 2.2 - - µs Er(1) TS_vbat(1)(2) 1. Guaranteed by design. 2. Shortest sampling time can be determined in the application by multiple iterations.
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Package information 7 STM32F303xB STM32F303xC Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 7.1 LQFP100 – 14 x 14 mm, low-profile quad flat package information Figure 39. LQFP100 – 14 x 14 mm, low-profile quad flat package outline 0.
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STM32F303xB STM32F303xC Package information Table 81. LQPF100 – 14 x 14 mm, low-profile quad flat package mechanical data (continued) Symbol inches(1) millimeters Min Typ Max Min Typ Max A2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 - 0.2 0.0035 - 0.0079 D 15.80 16.00 16.2 0.622 0.6299 0.6378 D1 13.80 14.00 14.2 0.5433 0.5512 0.5591 D3 - 12.00 - - 0.4724 - E 15.80 16.00 16.2 0.622 0.6299 0.6378 E1 13.80 14.
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Package information STM32F303xB STM32F303xC LQFP100 device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 41.
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STM32F303xB STM32F303xC 7.2 Package information LQFP64 – 10 x 10 mm, low-profile quad flat package information Figure 42. LQFP64 – 10 x 10 mm, low-profile quad flat package outline 0.25 mm GAUGE PLANE c A1 A A2 SEATING PLANE C A1 ccc C D D1 D3 K L L1 33 48 32 49 64 PIN 1 IDENTIFICATION E E1 E3 b 17 16 1 e 5W_ME_V3 1. Drawing is not to scale. Table 82.
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Package information STM32F303xB STM32F303xC Table 82. LQFP64 – 10 x 10 mm, low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max E1 - 10.00 - - 0.3937 - E3 - 7.50 - - 0.2953 - e - 0.50 - - 0.0197 - K 0° 3.5° 7° 0° 3.5° 7° L 0.45 0.60 0.75 0.0177 0.0236 0.0295 L1 - 1.00 - - 0.0394 - ccc - - 0.08 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 43.
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STM32F303xB STM32F303xC Package information LQFP64 device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 44.
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Package information 7.3 STM32F303xB STM32F303xC LQFP48 – 7 x 7 mm, low-profile quad flat package information Figure 45. LQFP48 – 7 x 7 mm, low-profile quad flat package outline c A1 A A2 SEATING PLANE C 0.25 mm GAUGE PLANE ccc C K A1 D L D1 L1 D3 36 25 37 24 48 E E1 E3 b 13 PIN 1 IDENTIFICATION 1 12 e 5B_ME_V2 1. Drawing is not to scale. Table 83. LQFP48 – 7 x 7 mm, low-profile quad flat package mechanical data Symbol 132/149 Downloaded from Arrow.com.
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STM32F303xB STM32F303xC Package information Table 83. LQFP48 – 7 x 7 mm, low-profile quad flat package mechanical data (continued) Symbol inches(1) millimeters Min Typ Max Min Typ Max E1 6.80 7.00 7.20 0.2677 0.2756 0.2835 E3 - 5.50 - - 0.2165 - e - 0.50 - - 0.0197 - L 0.45 0.60 0.75 0.0177 0.0236 0.0295 L1 - 1.00 - - 0.0394 - K 0° 3.5° 7° 0° 3.5° 7° ccc - - 0.08 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Package information STM32F303xB STM32F303xC LQFP48 device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 47.
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STM32F303xB STM32F303xC 7.4 Package information WLCSP100 - 0.4 mm pitch wafer level chip scale package information Figure 48. WLCSP100 – 100L, 4.166 x 4.628 mm 0.4 mm pitch wafer level chip scale package outline A1 BALL LOCATION A DETAIL A K BOTTOM VIEW SIDE VIEW FRONT VIEW DETAIL A ROTATED 90° A1 ORIENTATION REFERENCE aaa (4X) TOP VIEW WAFER BACK SIDE WLCSP100L_A01Q_ME_V1 1. Drawing is not to scale. DS9118 Rev 14 135/149 142 Downloaded from Arrow.com.
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Package information STM32F303xB STM32F303xC Table 84. WLCSP100 – 100L, 4.166 x 4.628 mm 0.4 mm pitch wafer level chip scale package mechanical data inches(1) millimeters Symbol Min Typ Max Typ Min Max A 0.525 0.555 0.585 0.0207 0.0219 0.0230 A1 - 0.17 - - 0.0067 - A2 - 0.38 - - 0.0150 - (2) - 0.025 - - 0.0010 - (3) Øb 0.22 0.25 0.28 - 0.0098 0.0110 D 4.166 4.201 4.236 - 0.1654 0.1668 E 4.628 4.663 4.698 - 0.1836 0.1850 e - 0.4 - - 0.
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STM32F303xB STM32F303xC Package information Figure 49. WLCSP100 – 100L, 4.166 x 4.628 mm 0.4 mm pitch wafer level chip scale package recommended footprint Dpad Dsm WLCSP100L_A01Q_FP_V1 Table 85. WLCSP100 recommended PCB design rules (0.4 mm pitch) Dimension Recommended values Pitch 0.4 mm Dpad 0.225 mm Dsm 0.290 mm Stencil thickness 0.1 mm DS9118 Rev 14 137/149 142 Downloaded from Arrow.com.
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Package information STM32F303xB STM32F303xC WLCSP100 device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 50. WLCSP100, 0.
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STM32F303xB STM32F303xC 7.5 Package information Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 24: General operating conditions on page 60.
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Package information 7.5.2 STM32F303xB STM32F303xC Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Section 8: Ordering information. Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature.
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STM32F303xB STM32F303xC Package information Example 2: High-temperature application Using the same rules, it is possible to address applications that run at high ambient temperatures with a low dissipation, as long as junction temperature TJ remains within the specified range. Assuming the following application conditions: Maximum ambient temperature TAmax = 115 °C (measured according to JESD51-2), IDDmax = 20 mA, VDD = 3.
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Ordering information 8 STM32F303xB STM32F303xC Ordering information Table 87.
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STM32F303xB STM32F303xC 9 Revision history Revision history Table 88. Document revision history Date Revision Changes 22-Jun-2012 1 Initial release 07-Sep-2012 2 Modified Features on cover page. Modified Table 2: STM32F301xx family device features and peripheral counts Added clock tree to Section 3.
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Revision history STM32F303xB STM32F303xC Table 88. Document revision history (continued) Date 05-Dec-2012 144/149 Downloaded from Arrow.com. Revision Changes 4 Updated first page Removed references to VDDSDx and VSSSD Added reference to PM0214 in Section 1 Moved Temp. sensor calibartion values toTable 79 and VREF calibration values to Table 29 Updated Table 3: STM32F303xx family device features and peripheral counts UpdatedSection 3.4: Embedded SRAM Updated Section 3.
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STM32F303xB STM32F303xC Revision history Table 88. Document revision history (continued) Date 08-Jan-2013 24-Jun-2013 13-Nov-2013 Revision Changes 5 Updated Vhys and Ilkg in Table 54: I/O static characteristics. Updated VIL(NRST), VIH(NRST), and VNF(NRST) in Table 57: NRST pin characteristics. Updated Table 70: ADC accuracy - limited test conditions, 100-pin packages and Table 64: ADC accuracy - limited test conditions 2).
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Revision history STM32F303xB STM32F303xC Table 88. Document revision history (continued) Date 18-Apr-2014 09-Dec-2014 29-Jan-2015 146/149 Downloaded from Arrow.com. Revision Changes 8 Updated Table 50: EMI characteristics conditions :3.3v replaced by 3.6V. 2 Updated Section 6.3.17: Communications interfaces I C interface. Updated Table 77: Operational amplifier characteristics adding TS_OPAMP_VOUT row. Updated Section 3.13: Fast analog-to-digital converter (ADC). updated Arm and Cortex trademark.
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STM32F303xB STM32F303xC Revision history Table 88. Document revision history (continued) Date 17-Apr-2015 11-Dec-2015 Revision Changes 11 Updated Section 7: Package information: with new package information structure adding 1 sub paragraph for each package. Updated Figure 41: LQFP100 – 14 x 14 mm, low-profile quad flat package top view example removing gate mark.
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Revision history STM32F303xB STM32F303xC Table 88. Document revision history (continued) Date 06-May-2016 30-Oct-2018 148/149 Downloaded from Arrow.com. Revision Changes 13 Updated Table 43: LSE oscillator characteristics (fLSE = 32.768 kHz) LSEDRV[1:0] bits. Updated Table 28: Embedded internal reference voltage VREFINT internal reference voltage (min and typ values). Updated Figure 5: STM32F303xB/STM32F303xC LQFP64 pinout replacing VSS by PF4.
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