Datasheet

Electrical characteristics STM32F302x6 STM32F302x8
98/138 DocID025147 Rev 7
Note: Refer to RM0365 Reference Manual I2S Section for more details about the sampling
frequency (Fs), fMCK, fCK, DCK values reflect only the digital peripheral behavior, source
clock precision might slightly change the values DCK depends mainly on ODD bit value.
Digital contribution leads to a min of (I2SDIV/(2*I2SDIV+ODD) and a max
(I2SDIV+ODD)/(2*I2SDIV+ODD) and Fs max supported for each mode/condition.
t
v(WS)
WS valid time Master mode - 20
ns
t
h(WS)
WS hold time Master mode 2 -
t
su(WS)
WS setup time Slave mode 0 -
t
h(WS)
WS hold time Slave mode 4 -
t
su(SD_MR)
Data input setup time
Master receiver 1 -
t
su(SD_SR)
Slave receiver 1 -
t
h(SD_MR)
Data input hold time
Master receiver 8 -
t
h(SD_SR)
Slave receiver 2.5 -
t
v(SD_ST)
Data output valid time
Slave transmitter (after enable edge) - 50
t
v(SD_MT)
Master transmitter (after enable
edge)
-22
t
h(SD_ST)
Data output hold time
Slave transmitter (after enable edge) 8 -
t
h(SD_MT)
Master transmitter (after enable
edge)
1-
1. Guaranteed by characterization results.
2. 256xFs maximum is 36 MHz (APB1 Maximum frequency)
Table 62. I2S characteristics
(1)
(continued)
Symbol Parameter Conditions Min Max Unit
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