Datasheet

DS6329 Rev 16 29/184
STM32F20xxx Functional overview
183
Figure 7. Regulator OFF / internal reset OFF
The following conditions must be respected:
• V
DD
must always be higher than V
CAP_1
and V
CAP_2
to avoid current injection between
power domains (see Figure 8).
• PA0 must be kept low to cover both conditions: until V
CAP_1
and V
CAP_2
reach 1.08 V,
and until V
DD
reaches 1.7 V.
• NRST must be controlled by an external reset controller to keep the device under reset
when V
DD
is below 1.7 V (see Figure 9).
In this mode, when the internal reset is OFF, the following integrated features are no more
supported:
• The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled.
• The brownout reset (BOR) circuitry is disabled.
• The embedded programmable voltage detector (PVD) is disabled.
• V
BAT
functionality is no more available and V
BAT
pin must be connected to VDD.
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