Datasheet

Functional overview STM32F20xxx
28/184 DS6329 Rev 16
Figure 6. Regulator OFF / internal reset ON
The following conditions must be respected:
• V
DD
must always be higher than V
CAP_1
and V
CAP_2
to avoid current injection between
power domains.
• If the time for V
CAP_1
and V
CAP_2
to reach 1.08 V is faster than the time for V
DD
to
reach 1.8 V, then PA0 must be kept low to cover both conditions: until V
CAP_1
and
V
CAP_2
reach 1.08 V and until V
DD
reaches 1.8 V (see Figure 8).
• Otherwise, If the time for V
CAP_1
and V
CAP_2
to reach 1.08 V is slower than the time for
V
DD
to reach 1.8 V, then PA0 must be asserted low externally (see Figure 9).
• If V
CAP_1
and V
CAP_2
go below 1.08 V and V
DD
is higher than 1.8 V, then a reset must
be asserted on PA0 pin.
Regulator OFF/internal reset OFF
On WLCSP64+2 package, this mode activated by connecting REGOFF to V
SS
and IRROFF
to V
DD
. IRROFF cannot be activated in conjunction with REGOFF. This mode is available
only on the WLCSP64+2 package. It allows to supply externally a 1.2
V voltage source
through V
CAP_1
and V
CAP_2
pins. In this mode, the integrated power-on reset (POR)/ power-
down reset (PDR) circuitry is disabled.
An external power supply supervisor must monitor both the external 1.2 V and the external
V
DD
supply voltage, and must maintain the device in reset mode as long as they remain
below a specified threshold. The V
DD
specified threshold, below which the device must be
maintained under reset, is 1.8
V. This supply voltage can drop to 1.7 V when the device
operates in the 0 to 70
°C temperature range. A comprehensive set of power-saving modes
allows the design of low-power applications.
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