Datasheet
Revision history STM32F20xxx
176/184 DS6329 Rev 16
22-Apr-2011
6
(continued)
Changed t
w(SCKH)
to t
w(SCLH)
, t
w(SCKL)
to t
w(SCLL)
, t
r(SCK)
to t
r(SCL)
, and
t
f(SCK)
to t
f(SCL)
in Table 52: I2C characteristics and in Figure 41: I2C
bus AC waveforms and measurement circuit.
Added Table 57: USB OTG FS DC electrical characteristics and
updated Table 58: USB OTG FS electrical characteristics.
Updated V
DD
minimum value in Table 62: Ethernet DC electrical
characteristics.
Updated Table 66: ADC characteristics and R
AIN
equation.
Updated R
AIN
equation. Updated Table 68: DAC characteristics.
Updated t
START
in Table 69: Temperature sensor characteristics.
Updated R typical value in Table 70: VBAT monitoring characteristics.
Updated Table 71: Embedded internal reference voltage.
Modified FSMC_NOE waveform in Figure 57: Asynchronous non-
multiplexed SRAM/PSRAM/NOR read waveforms. Shifted end of
FSMC_NEx/NADV/addresses/NWE/NOE/NWAIT of a half FSMC_CLK
period, changed t
d(CLKH-NExH
) to t
d(CLKL-NExH)
,
t
d(CLKH-AIV)
to t
d(CLKL-
AIV)
, t
d(CLKH-NOEH)
to t
d(CLKL-NOEH)
, and t
d(CLKH-NWEH)
to t
d(CLKL-NWEH)
,
and updated data latency from 1 to 0 in Figure 61: Synchronous
multiplexed NOR/PSRAM read timings, Figure 62: Synchronous
multiplexed PSRAM write timings, Figure 63: Synchronous non-
multiplexed NOR/PSRAM read timings, and Figure 64: Synchronous
non-multiplexed PSRAM write timings,
Changed t
d(CLKH-NExH
) to t
d(CLKL-NExH)
,
t
d(CLKH-AIV)
to t
d(CLKL-AIV)
,
t
d(CLKH-NOEH)
to t
d(CLKL-NOEH)
, t
d(CLKH-NWEH)
to t
d(CLKL-NWEH)
, and
modified t
w(CLK)
minimum value in Table 76, Table 77, Table 78, and
Table 79.
Updated note 2 in Table 72, Table 73, Table 74, Table 75, Table 76 ,
Table 77, Table 78, and Table 79.
Modified t
h(NIOWR-D)
in Figure 70: PC Card/CompactFlash controller
waveforms for I/O space write access.
Modified FSMC_NCEx signal in Figure 71: NAND controller waveforms
for read access, Figure 72: NAND controller waveforms for write
access, Figure 73: NAND controller waveforms for common memory
read access, and Figure 74: NAND controller waveforms for common
memory write access
Specified Full speed (FS) mode for Figure 89: USB OTG HS peripheral-
only connection in FS mode and Figure 90: USB OTG HS host-only
connection in FS mode.
Table 96. Document revision history (continued)
Date Revision Changes
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