Datasheet

Electrical characteristics STM32F20xxx
142/184 DS6329 Rev 16
PC Card/CompactFlash controller waveforms and timings
Figure 65 through Figure 70 represent synchronous waveforms, with Table 80 and Table 81
providing the corresponding timings. The results shown in these table are obtained with the
following FSMC configuration:
• COM.FSMC_SetupTime = 0x04;
• COM.FSMC_WaitSetupTime = 0x07;
• COM.FSMC_HoldSetupTime = 0x04;
• COM.FSMC_HiZSetupTime = 0x00;
• ATT.FSMC_SetupTime = 0x04;
• ATT.FSMC_WaitSetupTime = 0x07;
• ATT.FSMC_HoldSetupTime = 0x04;
• ATT.FSMC_HiZSetupTime = 0x00;
• IO.FSMC_SetupTime = 0x04;
• IO.FSMC_WaitSetupTime = 0x07;
• IO.FSMC_HoldSetupTime = 0x04;
• IO.FSMC_HiZSetupTime = 0x00;
• TCLRSetupTime = 0;
• TARSetupTime = 0;
In all timing tables, the T
HCLK
is the HCLK clock period.
t
d(CLKL-
NADVL)
FSMC_CLK low to FSMC_NADV low - 5 ns
t
d(CLKL-
NADVH)
FSMC_CLK low to FSMC_NADV high 6 - ns
t
d(CLKL-AV)
FSMC_CLK low to FSMC_Ax valid (x=16…25) - 0 ns
t
d(CLKL-AIV)
FSMC_CLK low to FSMC_Ax invalid (x=16…25) 8 - ns
t
d(CLKL-NWEL)
FSMC_CLK low to FSMC_NWE low - 1 ns
t
d(CLKL-NWEH)
FSMC_CLK low to FSMC_NWE high 1 - ns
t
d(CLKL-Data)
FSMC_D[15:0] valid data after FSMC_CLK low - 2 ns
t
d(CLKL-NBLH)
FSMC_CLK low to FSMC_NBL high 2 - ns
1. C
L
= 30 pF.
2. Guaranteed by characterization results, not tested in production.
Table 79. Synchronous non-multiplexed PSRAM write timings
(1)(2)
(continued)
Symbol Parameter Min Max Unit
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