Datasheet

DS6329 Rev 16 137/184
STM32F20xxx Electrical characteristics
183
Synchronous waveforms and timings
Figure 61 through Figure 64 represent synchronous waveforms, and Table 77 through
Table 79 provide the corresponding timings. The results shown in these tables are obtained
with the following FSMC configuration:
• BurstAccessMode = FSMC_BurstAccessMode_Enable;
• MemoryType = FSMC_MemoryType_CRAM;
• WriteBurst = FSMC_WriteBurst_Enable;
• CLKDivision = 1; (0 is not supported, see the STM32F20xxx/21xxx reference manual)
• DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
In all timing tables, the T
HCLK
is the HCLK clock period.
t
h(A_NWE)
Address hold time after FSMC_NWE high T
HCLK
– 0.5 - ns
t
h(BL_NWE)
FSMC_BL hold time after FSMC_NWE high T
HCLK
- 1 - ns
t
v(BL_NE)
FSMC_NEx low to FSMC_BL valid - 0.5 ns
t
v(Data_NADV)
FSMC_NADV high to Data valid - T
HCLK
+ 2 ns
t
h(Data_NWE)
Data hold time after FSMC_NWE high T
HCLK
– 0.5 - ns
1. C
L
= 30 pF.
2. Guaranteed by characterization results, not tested in production.
Table 75. Asynchronous multiplexed PSRAM/NOR write timings
(1)(2)
(continued)
Symbol Parameter Min Max Unit
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